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http://dx.doi.org/10.7471/ikeee.2017.21.2.153

A Study on GCNMOS-based ESD Protection Circuit Using Floating-Body Technique With Low Trigger Voltage  

Jeong, Jun-Mo (Dept. of Computer Science, Seokyeong University)
Publication Information
Journal of IKEEE / v.21, no.2, 2017 , pp. 150-153 More about this Journal
Abstract
In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.
Keywords
ESD; GGNMOS; GCNMOS; RC-network; Body floating;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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