Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Study on GCNMOS-based ESD Protection Circuit Using Floating-Body Technique With Low Trigger Voltage

Floating-Body기술을 이용한 낮은 트리거 전압을 갖는 GCNMOS 기반의 ESD 보호회로에 관한 연구

  • Jeong, Jun-Mo (Dept. of Computer Science, Seokyeong University)
  • Received : 2017.06.16
  • Accepted : 2016.06.30
  • Published : 2017.06.30
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Abstract

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

본 논문에서는 Floating기술을 이용한 GCNMOS 기반의 ESD(Electrostatic Discharge)보호회로를 제안한다. 제안된 보호회로의 특성 분석을 위해서 시놉시스사의 TCAD 시뮬레이션을 이용하였으며 기존의 GGNMOS, GCNMOS와 비교 분석하였다. 제안된 보호회로는 Gate coupling과 Body floating기술을 적용하였으며 기존 ESD보호회로인 GGNMOS, GCNMOS와 비교하여 더 낮은 4.86V의 트리거 전압 및 1.47ns의 짧은 턴-온 타임 특성을 갖는다.

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References

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