• Progress in Superconductivity
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• v.5 no.1
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.2
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• pp.24-27
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• 1975

A Synthesis method for multiple-input change transition-sensitive asynchronous sequential circuits is proposed. Both internal states and output states are synthesized from primitive flow tables. It is Btown that cur realization is faster than that of Chuang's. It is pointed out that Chuang's realization of output states contains malfunctions. In this paper, output stales are easily realized from primitive flaw table by the method of controlled excitation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.349-352
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• 2009

WBAN/USN systems are applied from the various environment. Therefore, it is coming to be important efficient use power and communication method. The present paper materialize Slave node system which get power from light energy. Also, it materialize Wake-up module and self-power-off circuit which use S-R Flip Flop for efficient using power. This system can be efficient using power at Slave node system. Also, it can be possible application of Self sustaining system by performance verification Wake-up module which determine system "on" without power and Self-power-off circuit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.109-111
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• 2002

We have demonstrated all-opticalflip-flop based on optical bistability in a SOA/DFB-SOA with broadband gain. Input signal with the wavelength of 1340.23 nm or 1680.93 nm and the current of about 98% of the lasing threshold is injected into theDFB-SOA. Current injected into SOA is 80 mA All-optical flip-flop has various applications such as all-optical memory, demultiplexing, packet-header buffering, and retiming.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.668-671
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• 2003

A concept of deadlock point of fuzzy sequential circuit is proposed. There are six cases of fuzzy sequential circuits of 1 state and 1 input variables with deadlock points. Examples of each case are shown both in a form of characteristic equation and in a graphical illustration. As fuzzy sequential circuit with 1 state and 1 input variables, D and T fuzzy flip-Hops are also characterized using the proposed concept. Thus one of the four types of D fuzzy Hip-Hops and T fuzzy Hip-flop have a deadlock point 1/2.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.4
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• pp.1232-1245
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• 2021

In this study, prediction of product sales as they relate to changes in temperature is proposed. This model uses long short-term memory (LSTM), which has shown excellent performance for time series predictions. For verification of the proposed sales prediction model, the sales of short pants, flip-flop sandals, and winter outerwear are predicted based on changes in temperature and time series sales data for clothing products collected from 2015 to 2019 (a total of 1,865 days). The sales predictions using the proposed model show increases in the sale of shorts and flip-flops as the temperature rises (a pattern similar to actual sales), while the sale of winter outerwear increases as the temperature decreases.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.240-243
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• 1999

This paper presents a data-dependent precharge suppression(DPS) D-flip-flop(DFF) with precharge suppression scheme according to data-transition probability The main feature of the DPS DFF is that precharge is suppressed when there is no data transition. The proposed DPS DFF consumes less power than the conventional Yuan-Svensson's true single phase clocking(TSPC) DFF when the data-transition probability is low. The simulation result shows that the power consumption is reduced by 42.2 % when the data-transition probability is 30%.