• 한국전기전자재료학회논문지
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• 제33권1호
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• pp.16-20
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• 2020

In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.

• 한국전기전자재료학회논문지
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• 제33권3호
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• pp.169-172
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• 2020

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is V_G=V_D, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.209-209
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.208-208
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2004년도 제27회 학술발표회 초록집
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• pp.69-70
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• 2004

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.107.1-107.1
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• 2014

We have developed and commercialize a time-of-flight - medium energy ion scattering spectrometry (TOF-MEIS) system (model MEIS-K120). MEIS-K120 adapted a large solid acceptance angle detector that results in high collection efficiency, minimized ion beam damage while maintaining a similar energy resolution. In addition, TOF analyzer regards neutrals same to ions which removes the ion neutralization problems in absolute quantitative analysis. A TOF-MEIS system achieves $7{\times}10^{-3}$ energy resolution by utilizing a pulsed ion beam with a pulse width 350 ps and a TOF delay-line-detector with a time resolution of about 85 ps. TOF-MEIS spectra were obtained using 100 keV $He^+$ ions with an ion beam diameter of $10{\mu}m$ with ion dose $1{\times}10^{16}$ in ordinary experimental condition. Among TOF-MEIS applications, we report the quantitative compositional profiling of 3~5 nm CdSe/ZnS QDs, As depth profile and substitutional As ratio of As implanted/annealed Si, Ionic Critical Dimension (CD) for FinFET, Direct Recoil (DR) analysis of hydrogen in diamond like carbon (DLC) and InxGayZnzOn on glass substrate.

• 한국전기전자재료학회논문지
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• 제33권2호
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• pp.88-92
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• 2020

Thermal effects in bulk and SOI FinFETs are briefly reviewed herein. Different techniques to measure these thermal effects are studied in detail. Self-heating effects show a strong dependency on geometrical parameters of the device, thereby affecting the reliability and performance of FinFETs. Mobility degradation leads to 7% higher current in bulk FinFETs than in SOI FinFETs. The lower thermal conductivity of SiO₂ and higher current densities due to a reduction in device dimensions are the potential reasons behind this degradation. A comparison of both bulk and SOI FinFETs shows that the thermal effects are more dominant in bulk FinFETs as they dissipate more heat because of their lower lattice temperature. However, these thermal effects can be minimized by integrating 2D materials along with high thermal conductive dielectrics into the FinFET device structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.76-81
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• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• 전기전자학회논문지
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• 제20권2호
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• pp.167-170
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• 2016

정적 램의 비트라인을 정밀하게 추적하는 감지증폭기의 enable 신호를 만들기 위해 replica bit-line 기술 (RBL)이 사용된다. 하지만, 공정으로 인한 문턱전압의 변화는 replica bit-line 회로에 흐르는 전류를 변화시키고 이는 감지증폭기의 enable 신호 생성 시간 ($T_{SAE}$)을 변화시키며, 결과적으로는 읽기 동작을 불안정하게 한다. 본 논문에서는 conventional replica bit-line delay ($RBL_{conv}$)구조 및 $T_{SAE}$ 변화를 감소시킬 수 있는 개선 구조인 dual replica bit-line delay (DRBD)구조와 multi-stage dual replica bit-line delay(MDRBD)구조를 소개하고, 14nm FinFET 공정, 동작전압 0.6V에서 각 기술들에 대한 읽기 성공률이 $6{\sigma}$를 만족하는 최대 on-cell 개수를 simulation을 통해 찾고 이때 각 구조에 대한 performance와 에너지를 비교했다. 그 결과, $RBL_{conv}$ 대비 DRBD와 MDRBD의 performance는 각각 24.4%와 48.3% 저하되고 에너지 소모는 각각 8%와 32.4% 감소된 것을 관찰하였다.

• Applied Microscopy
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• 제52권
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.