• Title/Summary/Keyword: fast linear annealing

Search Result 14, Processing Time 0.021 seconds

Eliminating Voids in Direct Bonded Si/Si3N4‖SiO2/Si Wafer Pairs Using a Fast Linear Annealing (직접접합 실리콘/실리콘질화막//실리콘산화막/실리콘 기판쌍의 선형가열에 의한 보이드 결함 제거)

  • Jung Youngsoon;Song Ohsung;Kim Dugjoong;Joo Youngcheol
    • Korean Journal of Materials Research
    • /
    • v.14 no.5
    • /
    • pp.315-321
    • /
    • 2004
  • The void evolution in direct bonding process of $Si/Si_3$$N_4$$SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

Bonding Property of Silicon Wafer Pairs with Annealing Method (열처리 방법에 따른 실리콘 기판쌍의 접합 특성)

  • 민홍석;이상현;송오성;주영창
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.16 no.5
    • /
    • pp.365-371
    • /
    • 2003
  • We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

Stress Evolution with Annealing Methods in SOI Wafer Pairs (열처리 방법에 따른 SOI 기판의 스트레스변화)

  • Seo, Tae-Yune;Lee, Sang-Hyun;Song, Oh-Sung
    • Korean Journal of Materials Research
    • /
    • v.12 no.10
    • /
    • pp.820-824
    • /
    • 2002
  • It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

A Study on the Thermal Characteristics of a 10 cm-diameter substrate for TMR devices by FLA Method (선형가열 법에 따른 TMR 소자용 직경 10cm 기판의 열적 특성에 관한 연구)

  • 송오성;이영민;주영철
    • Journal of the Korean Magnetics Society
    • /
    • v.11 no.2
    • /
    • pp.78-83
    • /
    • 2001
  • The thermal characteristics of TMR devices by using Fast Linear Annealing method has been studied. A computer program that employs the finite differential method has been developed to simulate the temperature distribution of a diameter of 4" silicon wafer, which is subjected to radiation heat from the halogen lamp. We adopted the temperature of 350$\^{C}$, which is the highest temperature usually used in annealing for magnetic thin films. We changed moving velocity of the lamp from 0.05 mm/sec to 1 mm/sec. The moving velocity of halogen lamp has less effect on the local peak temperature of the sample only about 40$\^{C}$. Therefore, we may be able to anneal TMR devices in such short time of 1 minute and 40 seconds per one wafer, using the Fast Linear Annealing method.

  • PDF

Direct Bonding of Heterogeneous Insulator Silicon Pairs using Various Annealing Method (열처리 방법에 따른 이종절연층 실리콘 기판쌍의 직접접합)

  • 송오성;이기영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.16 no.10
    • /
    • pp.859-864
    • /
    • 2003
  • We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

Direct Bonding of SillSiO2/Si3N4llSi Wafer Fairs with a Fast Linear Annealing (선형가열기를 이용한 SillSiO2/Si3N4llSi 이종기판쌍의 직접접합)

  • 이상현;이상돈;송오성
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.15 no.4
    • /
    • pp.301-307
    • /
    • 2002
  • Direct bonded SOI wafer pairs with $Si ll SiO_2/Si_3N_4 ll Si$ the heterogeneous insulating layers of SiO$_2$-Si$_3$N$_4$are able to apply to the micropumps and MEMS applications. Direct bonding should be executed at low temperature to avoid the warpage of the wafer pairs and inter-diffusion of materials at the interface. 10 cm diameter 2000 ${\AA}-SiO_2/Si(100}$ and 560 $\AA$- ${\AA}-Si_3N_4/Si(100}$ wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were pre- mated with facing the mirror planes by a specially designed aligner in class-100 clean room immediately. We employed a heat treatment equipment so called fast linear annealing(FLA) with a halogen lamp to enhance the bonding of pre mated wafers We kept the scan velocity of 0.08 mm/sec, which implied bonding process time of 125 sec/wafer pairs, by varying the heat input at the range of 320~550 W. We measured the bonding area by using the infrared camera and the bonding strength by the razor blade clack opening method, respective1y. It was confirmed that the bonding area was between 80% and to 95% as FLA heat input increased. The bonding strength became the equal of $1000^{\circ}C$ heat treated $Si ll SiO_2/Si_3N_4 ll Si$ pair by an electric furnace. Bonding strength increased to 2500 mJ/$\textrm{m}^2$as heat input increased, which is identical value of annealing at $1000^{\circ}C$-2 hr with an electric furnace. Our results implies that we obtained the enough bonding strength using the FLA, in less process time of 125 seconds and at lowed annealing temperature of $400^{\circ}C$, comparing with the conventional electric furnace annealing.

A Maintenance Design of Connected-(r, s)-out-of-(m, n) F System Using Simulated Annealing (시뮬레이티드 어닐링을 이용한(m, n)중 연속(r,s) : F 시스템의 정비모형)

  • Lee, Sangheon;Kang, Youngtai;Shin, Dongyeul
    • Journal of Korean Institute of Industrial Engineers
    • /
    • v.34 no.1
    • /
    • pp.98-107
    • /
    • 2008
  • The purpose of this paper is to present an optimization scheme that aims at minimizing the expected cost per unittime. This study considers a linear connected-(r, s)-ouI-of-(m, n):f lattice system whose components are orderedlike the elements of a linear (m, n)-matrix. We assume that all components are in the state 1 (operating) or 0(failed) and identical and s-independent. The system fails whenever at least one connected (r, s)-submatrix offailed components occurs. To find the optimal threshold of maintenance intervention, we use a simulatedannealing(SA) algorithm for the cost optimization procedure. The expected cost per unit time is obtained byMonte Carlo simulation. We also has made sensitivity analysis to the different cost parameters. In this study,utility maintenance model is constructed so that minimize the expense under full equipment policy throughcomparison for the full equipment policy and preventive maintenance policy. The full equipment cycle and unitcost rate are acquired by simulated annealing algorithm. The SA algorithm is appeared to converge fast inmulti-component system that is suitable to optimization decision problem.

Optimal Location of FACTS Devices Using Adaptive Particle Swarm Optimization Hybrid with Simulated Annealing

  • Ajami, Ali;Aghajani, Gh.;Pourmahmood, M.
    • Journal of Electrical Engineering and Technology
    • /
    • v.5 no.2
    • /
    • pp.179-190
    • /
    • 2010
  • This paper describes a new stochastic heuristic algorithm in engineering problem optimization especially in power system applications. An improved particle swarm optimization (PSO) called adaptive particle swarm optimization (APSO), mixed with simulated annealing (SA), is introduced and referred to as APSO-SA. This algorithm uses a novel PSO algorithm (APSO) to increase the convergence rate and incorporate the ability of SA to avoid being trapped in a local optimum. The APSO-SA algorithm efficiency is verified using some benchmark functions. This paper presents the application of APSO-SA to find the optimal location, type and size of flexible AC transmission system devices. Two types of FACTS devices, the thyristor controlled series capacitor (TCSC) and the static VAR compensator (SVC), are considered. The main objectives of the presented method are increasing the voltage stability index and over load factor, decreasing the cost of investment and total real power losses in the power system. In this regard, two cases are considered: single-type devices (same type of FACTS devices) and multi-type devices (combination of TCSC, SVC). Using the proposed method, the locations, type and sizes of FACTS devices are obtained to reach the optimal objective function. The APSO-SA is used to solve the above non.linear programming optimization problem for better accuracy and fast convergence and its results are compared with results of conventional PSO. The presented method expands the search space, improves performance and accelerates to the speed convergence, in comparison with the conventional PSO algorithm. The optimization results are compared with the standard PSO method. This comparison confirms the efficiency and validity of the proposed method. The proposed approach is examined and tested on IEEE 14 bus systems by MATLAB software. Numerical results demonstrate that the APSO-SA is fast and has a much lower computational cost.