• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.649-658
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• 1997

Database management systems(DMBS)using bolatile memory shluld have a recovery function to protect data against system failutes.Recovery requires much overhead in transaction proessing and is one of the great factors that deteriorate the system performance.Recently, there have been a lot of studies on database systems with nonbolatile memory to enhance the performance.A nonbolatile memory called DFeRAM is one of the promising memory devices of the future technology, but this device does not support fine-franularity licking.In this paper, we present a dual plane FeRAM(DFeRAM)architecture to support the fine-granularity locking.We also propose a recovery algorithm for the database system with the DFeRAM based on a shadow paging methed.In order to analze the performance of the proposed algorithm, we present an analytical model and analyze the performance using the moedl.

• Journal of Information Processing Systems
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• v.15 no.1
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• pp.151-158
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• 2019

With the recent advances of memory technologies, high-performance non-volatile memories such as non-volatile dual in-line memory module (NVDIMM) have begun to be used as an addition or an alternative to server-side storages. When these memory bus-connected storages (MBSs) are installed over non-uniform memory access (NUMA) servers, the distance between NUMA nodes and MBSs is one of the crucial factors that influence file processing performance, because the access latency of a NUMA system varies depending on its distance from the NUMA nodes. This paper presents the design and implementation of a high-performance logical volume manager for MBSs, called MBS-LVM, when multiple MBSs are scattered over a NUMA server. The MBS-LVM consolidates the address space of each MBS into a single global address space and dynamically utilizes storage spaces such that each thread can access an MBS with the lowest latency possible. We implemented the MBS-LVM in the Linux kernel and evaluated its performance by porting it over the tmpfs, a memory-based file system widely used in Linux. The results of the benchmarking show that the write performance of the tmpfs using MBS-LVM has been improved by up to twenty times against the original tmpfs over a NUMA server with four nodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• Structural Engineering and Mechanics
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• v.89 no.4
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• pp.375-381
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• 2024

In this paper, Eringen's nonlocal thermoelasticity is constructed to study wave propagation in a rotating two-temperature thermoelastic half-space. The problem is applied in the context of the dual-phase-lag (Dual) model, coupled theory (CD), and Lord-Shulman (L-S) theory. Using suitable non-dimensional fields, the harmonic wave analysis is used to solve the problem. Comparisons are carried with the numerical values predicted in the absence and presence of the gravity field, a nonlocal parameter as well as rotation. The present study is valuable for the analysis of nonlocal thermoelastic problems under the influence of the gravity field, mechanical force, and rotation.