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Duty Cycle-Corrected Analog Synchronous Mirror Delay for High-Speed DRAM  

Choi Hoon (Hynix Semiconductor, Memory R&D Division Design)
Kim Joo-Seong (School of Information and Communicaiton Engineering, Sungunkwan University)
Jang Seong-Jin (Samsung Electronics, Memory Division)
Lee Jae-Goo (School of Information and Communicaiton Engineering, Sungunkwan University)
Jun Young-Hyun (Samsung Electronics, Memory Division)
Kong Bai-Sun (School of Information and Communicaiton Engineering, Sungunkwan University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.9, 2005 , pp. 29-34 More about this Journal
Abstract
This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.
Keywords
Clock synchronization; synchronous mirror delay; dual edge triggering; duty cycle correction;
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