• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.458-466
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• 2012

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.582-586
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• 2013

In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.

• Journal of IKEEE
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• v.15 no.2
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• pp.143-148
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• 2011

MOS (Metal-Oxide Semconductor) devices among the most sensistive of all semiconductors to radiation, in particular ionizing radiation, showing much change even after a relatively low dose. The necessity of a radiation dosimeter robust enough for the working environment has increased in the fields of aerospace, radio-therapy, atomic power plant facilities, and other places where radiation exists. The power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) has been tested for use as a gamma radiation dosimeter by measuring the variation of threshold voltage based on the quantity of dose, and a maximum total dose of 30 krad exposed to a $^{60}Co$ ${\gamma}$-radiation source, which is sensitive to environment parameters such as temperature. The gate oxide structures give the main influence on the changes in the electrical characteristics affected by irradiation. The variation of threshold voltage on the operating temperature has caused errors, and needs calibration. These effects can be overcome by adjusting gate oxide thickness and implanting impurity at the surface of well region in MOSFET.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.392-395
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• 2003

For the first time, the new dual trench gate Emitter Switched Thyristor is proposed for eliminating snap-back effect which leads to a lot of serious problems of device applications. Also, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in the proposed EST structure, allowing higher maximum controllable current densities for ESTs. Moreover, the new dual trench gate allows homogenous current distribution throughout device and preserves the unique feature of the gate controlled current saturation of the thyristor current. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $354/{\S}^2$, respectively. But the proposed EST exhibits snap-back with the anode voltage and current density 0.93V and $58A/{\S}^2$, respectively. Saturation current density of the proposed EST at anode voltage 6.11V is $3797A/{\S}^2$. The characteristics of 700V forward blocking of the proposed EST obtained from two dimensional numerical simulations (MEDICI) is described and compared with that of the conventional EST.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1633-1640
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• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.