Browse > Article

Feasibility Study of Non-volatile Memory Device Structure for Nanometer MOSFET  

Jeong, Ju Young (Department of Electronic Engineering, The University of Suwon)
Publication Information
Journal of the Semiconductor & Display Technology / v.14, no.2, 2015 , pp. 41-45 More about this Journal
Abstract
From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.
Keywords
floating body effect; finFET; non-volatile memory; dual gate MOSFET; simulation; kink effect; capacitorless DRAM; SOI;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Jacques Gautier', Keith A. Jenkins, Jack Y.- C. Sun, "Body Charge Related Transient Effects In Floating Body So1 Nmosfet's," in IEDM'95, pp. 623-626, 1995.
2 S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, "A capacitor-less 1T-DRAM cell," IEEE Electron Device Lett., vol. 23, no. 2, pp. 85-87, Feb. 2002.   DOI
3 E. Yoshida and T. Tanaka, "A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory," in IEDM Tech. Dig., 2003, pp. 37.6.1-37.6.4.
4 T. Tanaka, E. Yoshida, and T. Miyashita, "Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM," in IEDM Tech. Dig., 2004, pp. 919-922.
5 Takeshi Hamamoto and Takashi Ohsawa, "Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond," in ESSDERC 2008, pp. 25-29.
6 Viktor Sverdlov and Siegfried Selberherr, "Modeling Floating Body Z-RAM Storage Cells," PROC. 27th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2010), NIS, SERBIA, 16-19 MAY, 2010.
7 Mark R. Pinto; kent smith; Muhammad Alam; Steven Clark; Xufeng Wang; Gerhard Klimeck; Dragica Vasileska (2014), "Padre," https://nanohub.org/resources/padre. (DOI: 10.4231/D30C4SK7Z).
8 Shaikh S. Ahmed; Saumitra Raj Mehrotra; SungGeun Kim; Matteo Mannino; Gerhard Klimeck; Dragica Vasileska; Xufeng Wang; Himadri Pal; Gloria Wahyu Budiman (2014), "MOSFet," https://nanohub.org/resources/mosfet. (DOI: 10.4231/D3Q23R14Z).