• Geotechnical Engineering
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• v.8 no.1
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• pp.67-80
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• 1992

An analytical solution method is presented to determine the radius of influence circle of a sand 4rain well(i.e., spacing between the sand drain wells) required in the design under various types of construction loading. The proposed method deals with a sand drain well having a smeared zone at the periphery of the drain well as well as flow resistance in the drain well. The method proposed in the present study is made based on the modification of 01son's solution which deals with a single ramp loading without considering smeard zone effect as well as flow resistance in the drain well. Further, the effects of various design paramenters on the drain spacing are analyzed using the proposed method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.38-45
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• 1993

In this study, the degradation characteristics of drain output resis-tance was described due to hot electron effects. An semi-empirical model for the degraded drain output resistance was derived from the measured device characteristics. The suggested model was verified from the measured data and the device parameter dependence was also analyzed. The degradation of drain output resistance was increased with stress time and had linear relationship with the degradation of drain current. The device lifetime which was defined by failure criteria of drain output resistance (such as $\Delta$ro/roo=5%) was equivalent to that of failure criteria of drain current (such as $\Delta$ID/ID=5%)

• Proceedings of the Korean Geotechical Society Conference
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• 2010.03a
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• pp.1256-1263
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• 2010

Suction Drain Method is soft ground improvement technique, in which a vacuum pressure can be directly applied to the Vertical Drain Board to promote consolidation and strengthening the soft ground. This method does not require a surcharge load, different to embankment or Preloading Method. In this study, ground improvement efficiency of suction drain method was estimated when duplex loading pressure with vacuum and pressure. During suction drain method process, surface settlement and pore pressure were monitored, and cone resistance test as well as water content were also measured after the completion of Suction Drain Method treatment.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 1998.10a
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• pp.438-443
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• 1998

In this study, compared the degree of consoildation of vertical drain considering variation of smear effect and well resistance with that of hyperbolic and curve fitting method. It applied Barren, Yoshikuni, Hansbo, Onoue's theory for the consolidation of vertical drain, and compared differences of theoretical curve by comparing with measured value, and finded out the extent of smear effect and well resistance.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1797-1799
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• 2000

A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.67-75
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• 2013

In this paper, an analytical model is presented for the source/drain parasitic resistance of FinFET. The parasitic resistance is a important part of a total resistance in FinFET because of current flow through the narrow fin. The model incorporates the contribution of contact and spreading resistances considering three-dimensional current flow. The contact resistance is modeled taking into account the current flow and parallel connection of dividing parts. The spreading resistance is modeled by difference between wide and narrow and using integral. We show excellent agreement between our model and simulation which is conducted by Raphael, 3D numerical field solver. It is possible to improve the accuracy of compact model such as BSIM-CMG using the proposed model.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.533-536
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• 1998

The electrical characteristics of NMOSFETs with asymmetrical source/drain regions have been expermentally investigated using test devices fabricated by $0.35\mu\textrm{m}$ CMOS technology. The performance degradation for asymmetric transistor and its causes are analyzed. The parasitic resistances, such as series resistance of active regions and silicide junction contact resistance, are distributed in parallel along the channel. Depending on source/drain geometry, the array of those resistances is changed, that results the various electrical properties.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.2
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• pp.235-238
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• 2008

This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.