Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Modeling of Parasitic Source/Drain Resistance in FinFET Considering 3D Current Flow

3차원적 전류 흐름을 고려한 FinFET의 기생 Source/Drain 저항 모델링

  • An, TaeYoon (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 안태윤 (성균관대학교 정보통신대학) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 김소영 (성균관대학교 정보통신대학)
  • Received : 2013.06.23
  • Published : 2013.10.25
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Abstract

In this paper, an analytical model is presented for the source/drain parasitic resistance of FinFET. The parasitic resistance is a important part of a total resistance in FinFET because of current flow through the narrow fin. The model incorporates the contribution of contact and spreading resistances considering three-dimensional current flow. The contact resistance is modeled taking into account the current flow and parallel connection of dividing parts. The spreading resistance is modeled by difference between wide and narrow and using integral. We show excellent agreement between our model and simulation which is conducted by Raphael, 3D numerical field solver. It is possible to improve the accuracy of compact model such as BSIM-CMG using the proposed model.

본 논문에서는 RSD(Raised Source/Drain)구조를 가지는 FinFET에서 3차원적 전류 흐름을 고려한 소스와 드레인의 해석적 저항모델을 제시한다. FinFET은 Fin을 통해 전류가 흐르기 때문에 소스/드레인의 기생저항이 크고 채널을 포함한 전체저항에서 중요한 부분을 차지한다. 제안하는 모델은 3차원적 전류흐름을 고려하여 contact부터 channel 직전 영역까지의 소스/드레인 저항을 나타내며 contact저항과 spreading저항의 합으로 이루어져 있다. Contact저항은 전류의 흐름을 고려한 가이드라인을 통해 작은 저항의 병렬합으로 모델링되고 spreading저항은 적분을 통해 구현했다. 제안된 모델은 3D numerical solver인 Raphael의 실험결과를 통해 검증했다. 본 연구에서 제안된 기생저항 모델을 BSIM-CMG와 같은 압축모델에 구현하여 DC 및 AC 성능 예측의 정확도를 높일 수 있을 것이다.

Keywords

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