Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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A SOI LDMOS with Trench Drain and Graded Gate

트렌치 드레인과 경사진 게이트를 갖는 SOI LDMOS

  • Kim, Sun-Ho (Department of Molecular Science & Technology, Ajou University) ;
  • Choi, Yearn-Ik (Department of Molecular Science & Technology, Ajou University)
  • 김선호 (아주대학교 분자과학기술학과) ;
  • 최연익 (아주대학교 분자과학기술학과)
  • Published : 2000.07.17
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Abstract

A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

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