• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
• /
• pp.317-320
• /
• 2000

In this paper, a 0.5W, 2GHz high-efficiency class A power amplifier using the dynamic bias control is proposed. First of all, the drain bias control amplifier is analyzed theoretically and designed with commercial devices. Simulation results show that the proposed amplifier has a significant improved efficiency, compared to fixed bias power amplifier.

• 한국산업정보학회:학술대회논문집
• /
• 한국산업정보학회 2002년도 춘계학술대회 논문집
• /
• pp.195-199
• /
• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• 전자공학회논문지
• /
• 제52권4호
• /
• pp.49-55
• /
• 2015

기존의 BSIM4 모델과 다이오드를 사용한 BSIM4 Macro 모델의 바이어스 종속 게이트-드레인 오버렙 캐패시턴스 $C_{gdo}$ 시뮬레이션의 부정확성에 대하여 자세히 분석하였다. 이러한 Macro 모델은 기존의 BSIM4 모델보다 더 정확하지만 선형영역에서 사용될 수 없음을 발견하였다. 기존 모델들의 부정확성을 제거하기 위해서 물리적인 바이어스 종속 $C_{gdo}$ 모델 방정식을 사용한 새로운 BSIM4 Macro 모델을 제안하였고 전체 바이어스 영역에서 유효함을 입증하였다.

• 전자공학회논문지A
• /
• 제32A권6호
• /
• pp.41-50
• /
• 1995

A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

• 한국전자파학회논문지
• /
• 제26권6호
• /
• pp.593-596
• /
• 2015

본 논문은 무선전력전송 시스템에 활용할 수 있도록 낮은 드레인 전압에서 높은 효율을 가지는 class E 전력증폭기를 설계하였다. 붕괴전압이 40 V인 Si MOSFET을 이용하여 드레인 바이어스 전압이 12.5 V인 13.56 MHz 전력증폭기를 설계하였다. 출력 전력 및 효율을 개선하기 위하여 품질계수가 우수한 솔레노이드 인덕터를 제작하여 출력 정합회로에 사용하였다. 발진 방지와 간단한 회로 구성을 위하여 인덕터와 저항으로 입력 정합회로를 구성하였다. 측정 결과, 제작된 전력증폭기는 13.56 MHz에서 38.6 dBm의 출력전력과 16.6 dB의 전력이득, 그리고 89.3 %의 높은 전력부가효율을 보였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
• /
• pp.86-89
• /
• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1992년도 하계학술대회 논문집 B
• /
• pp.825-828
• /
• 1992

In this paper, a Hybrid method for an effective channel length($L_{eff}$) on lightly doped drain(LDD) MOSFET's is proposed. In order to investigate the difference of the gate bias and substrate bias defendence of the $L_{eff}$ among various LDD structures, the $L_{eff}$ of the LDD's are extensively examined using simulations and measurement. one group is proposed for conventional MOSFET and the other group Is proposed for LDD MOSFET. It is shown that the $V_{bs}$-dependence of the n-region is different from $V_{gs}$-dependence of it.

• Journal of Electrical Engineering and Technology
• /
• 제9권6호
• /
• pp.2079-2088
• /
• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
• /
• pp.1172-1175
• /
• 2007

We have investigated the threshold voltage shifts(${\Delta}Vth$) and drain current level shift (${\Delta}Ids$) in subthreshold region of a-Si:H TFTs induced by DC Bias (Vgs and Vds) - Temperature stress (BTS) condition. We plotted the transfer curves and the ${\Delta}Vth$ contour maps as Vds-Vds stress bias and Temperature to examine the severe damage cases on TFTs. Also, by drawing out the time-dependent transfer curve (Ids-Vgs) in the region of $10^{-8}\;{\sim}\;10^{-13}$ (A) current level, we can estimate the failure time of TFTs in a operating condition.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.295-298
• /
• 1999

AlGaAs/InGaAs power P-HEMTS (Pseudo-morphic High Electron Mobility Transistors) with 1.0-${\mu}{\textrm}{m}$ gate length for PCS applications have been fabricated. We adopted single heterojunction P-HEMT structure with two Si-delta doped layer to obtain higher current density. It exhibits a maximum current density of 512㎃/mm, an extrinsic transconductance of 259mS/mm, and a gate to drain breakdown voltage of 12.0V, respectively. The device exhibits a power density of 657㎽/mm, a maximum power added efficiency of 42.1%, a linear power gain of 9.85㏈ respectively at a drain bias of 6.0V, gate bias of 0.6V and an operation frequency of 1.765㎓.