• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.283-284
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• 2012

In this work, a special technique called dielectric filling was carried out in order to reduce sub-threshold leakage current inside double-gated n-channel MOSFET. This calibration was done by using SILVACO Atlas(TCAD), and the result showed quite a good performance compared to the conventional double-gate MOSFET.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.279-287
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• 1993

In this paper, double laxity threshold MLT(Minimum Laxity Threshold) algorithm and double queue threshold QLT(Queue Length Threshold) algorithm are proposed as DPS(Dynamic Priority Scheduling) techniques for advanced processing of multiple class traffics. Also, the performance of the proposed algorithms is analyzed by a computer simulation. According to the simulation results, it can be shown that the proposed double laxity threshold ML T algorithm advances the processing performance versus ML T algorithm for 2 or more classes delay sensitive traffics, and that double queue length threshold QL T algorithm provides more efficient performance than QL T for 2 or more classes of non real time traffics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.2
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• pp.129-135
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• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2939-2945
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.243-249
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• 2010

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.2
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• pp.104-109
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• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2183-2188
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• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.1-6
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• 2008

A compact analytical model of the threshold voltage for long-channel Asymmetric Double-Gate(ADG) MOSFET is presented. In contrast to the previous models, channel doping and carrier quantization are taken into account. A more compact model is derived by utilizing the potential distribution linearity characteristic of silicon film at threshold. The accuracy of the model is verified by comparisons with numerical simulations for various silicon film thickness, channel doping concentration and oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.903-908
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• 2015

This paper has analyzed threshold voltage shift for doping profile of asymmetric double gate(DG) MOSFET. Ion implantation is usually used in process of doping for semiconductor device and doping profile becomes Gaussian distribution. Gaussian distribution function is changed for projected range and standard projected deviation, and influenced on transport characteristics. Therefore, doping profile in channel of asymmetric DGMOSFET is affected in threshold voltage. Threshold voltage is minimum gate voltage to operate transistor, and defined as top gate voltage when drain current is $0.1{\mu}A$ per unit width. The analytical potential distribution of series form is derived from Poisson's equation to obtain threshold voltage. As a result, threshold voltage is greatly changed by doping profile in high doping range, and the shift of threshold voltage due to projected range and standard projected deviation significantly appears for bottom gate voltage in the region of high doping concentration.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1475-1484
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• 1994

In this paper, a priority scheduling algorithm with double threshold and a traffic control mechanism with hysteresis effect are proposed. The double threshold priority scheduling is studied based on HOL and QLT. The hysteresis effect traffic control is specified by hysteresis effect QLT and traffic rate control. According to the simulation results, it can be shown that the proposed dynamic priority scheduling brings better processing performance than the existing QLT algorithm. And the results demonstrate that QLT and traffic rate control with hysteresis effect enhance the performance in comparison with those of single threshold.