• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.192-198
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• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권3호
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• pp.116-121
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• 2006

Most high-k materials are well known not to be etched easily, Some problems such as low etch rate poor sidewall angle, plasma damage, and process complexity were emerged from the high-density DRAM fabrication. Chemical mechanical polishing (CMP) by a damascene process was proposed to pattern this high-k material was polished with some commercial silica slurry as a function of pH variation. Sufficient removal rate with adequate selectivity to realize the pattern mask of tera-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible. The planarization was also achieved for the subsequent multi-level processes. Our new CMP approach will provide a guideline for effective patterning of high-k material by CMP technique.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.63-68
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• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• 한국인터넷방송통신학회논문지
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• 제20권5호
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• pp.151-156
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• 2020

주기적인 사다리꼴 격자구조에서 광 신호의 회절 특성과 테이퍼 측면의 중요한 효과를 분석하기 위하여, 처음으로 격자구조의 Toeplitz 유전율 tensor를 2D spatial Fourier 급수로 정의하고 공식화하였다. 그때 각 층에서의 필드들은 고유치 문제에 기초하여 표현하였으며, 완전한 해는 적절한 경계 값 문제에 의존하는 모드 전송선로 이론 (MTLT)을 사용하여 정확하게 유도하였다. 이에 기초하여, 사다리꼴 형태의 굴절률 분포를 갖는 격자구조의 테이퍼 측면 프로파일이 서브 파장 격자 반사기 설계에 어떠한 영향을 미치는지 자세하게 수치해석 하였다. 사다리꼴 격자구조의 회절특성에 기초한 수치해석 결과, 테이퍼 측벽 프로파일은 반사 대역폭, 평균 반사율, 그리고 밴드 에지를 결정하는 데 중요한 역할을 하는 것으로 나타났다.

• Journal of Information Display
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• 제11권2호
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• pp.84-90
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• 2010

This paper presents the effects of a dielectric layer and an electrolyte on the driving performance of an electrowetting on dielectric (EWOD)-based liquid lens. The range of tunable focal length of the EWOD-based liquid lens was highly dependent on the conditions of the dielectric layer, which included an inorganic oxide layer and an organic hydrophobic layer. Moreover, experiments on the physical and optical durability of electrolyte by varying temperature conditions, were conducted and their results were discussed. Finally, the lens with a truncated-pyramid silicon cavity having a sidewall dielectrics and electrode was fabricated by anisotropic etching and other micro-electromechanical systems (MEMS) technologies in order to demonstrate its performance. The lens with $0.6-{\mu}m$-thick $SiO_2$ layer and 10 wt% LiCl-electrolyte exhibited brilliant focal-length tunability from infinity to 3.19 mm.

• Transactions on Electrical and Electronic Materials
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• 제1권3호
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• pp.14-17
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• 2000

Giga bit dynamic random access memory(DRAM) requires the capacitor of high dielectric films. Some metal oxides films have been proposed as the dielectric material . And Pt is one of the most promising electrode materials. However very little has been done in developing the etching technologoy Pt film. Therefore, it is the first priority to develop the technology for plasma etching of Pt film. In this study, the dry etching of Pt film was investigated in Inductively Coupled Plasma(ICP) etching system with Cl$_2$/Ar and HBr/Cl$_2$/Ar gas mixing. X-ray photoelectron spectroscopy (XPS) was used in analysis of sidewall residues for the understanding of etching mechanism. We found the etch residues on the pattern sidewall is mainly Pt-Pt, Pt-Cl and Pt-Br compounds, Etch profile was observed by Scanning Electron Spectroscopy(SEM) . The etch rate of Pt film at 10%, Cl$_2$/90% Ar gas mixing ration was higher than at 100%. Ar. Addition of HBr to Cl$_2$/Ar as an etching gas led to generally higher selectivity to SiO$_2$. And the etch residues were reduced at 5% HBr/5% Cl$_2$/90% Ar gas mixing ration. These pages provide you with an examples of the layout and style which we wish you to adopt during the preparation of your paper, Make the width of abstract to be 14cm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.162-168
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• 2006

To fabricate nanometer scale InGaAs HEMTs, we have successfully developed various novel nano-patterning techniques, including sidewall-gate process and e-beam resist flowing method. The sidewall-gate process was developed to lessen the final line length, by means of the sequential procedure of dielectric re-deposition and etch-back. The e-beam resist flowing was effective to obtain fine line length, simply by applying thermal excitation to the semiconductor so that the achievable final line could be reduced by the dimension of the laterally migrated e-beam resist profile. Applying these methods to the device fabrication, we were able to succeed in making 30nm $In_{0.7}Ga_{0.3}As$ HEMTs with excellent $f_T$ of 426GHz. Based on nanometer scale InGaAs HEMT technology, several high performance millimeter-wave integrated circuits have been successfully fabricated, including 77GHz MMIC chipsets for automotive radar application.

• 전자공학회논문지D
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• 제34D권7호
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• pp.15-22
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• 1997

A 10Gbit/s limiting amplifier IC for optical transmission system was implemented with AlGaAs HBT (heterojunction bipolar transistor) technology. HBTs with 2x10.mu. $m^{2}$ and 6x20.mu. $m^{2}$ emitter size were used. The HBT structures are based on metal-organic chemical vapor deposition (MOCVD) epitxy and employ a mesa structure with self-aligned emitter/base and sidewall dielectric passivation. IC was designed to support differnetial input and output. Small signal performance of the packaged IC showed 26dB gain and $f_{3dB}$ of 8GHz. A single ouput has 800m $V_{p-p}$ swing with more than 26dB dynamic range. The performance of the limiting amplifier was verified through single mode fiber320km transmission link test.est.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.113-114
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• 2005

Sufficient removal rate with adequate selectivity to realize the pattern mask of tetra-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained by chemical mechanical polishing (CMP) with commercial silica slurry as a function of pH variation. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible.