• Title/Summary/Keyword: delta sigma modulator

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A Hybrid Audio ${\Delta}{\Sigma}$ Modulator with dB-Linear Gain Control Function

  • Kim, Yi-Gyeong;Cho, Min-Hyung;Kim, Bong-Chan;Kwon, Jong-Kee
    • ETRI Journal
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    • v.33 no.6
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    • pp.897-903
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    • 2011
  • A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

Mixed CT/DT Cascaded Sigma-Delta Modulator

  • Lee, Kye-Shin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.4
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    • pp.233-239
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    • 2009
  • A mixed CT/DT 2-1 cascaded ${\Sigma\Delta}M$ which includes a first stage CT ${\Sigma\Delta}M$ and a second stage mismatch insensitive two-channel time-interleaved DT ${\Sigma\Delta}M$ is proposed. With this approach, the advantages of both CT and DT ${\Sigma\Delta}Ms$ including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The two-channel time-interleaved ${\Sigma\Delta}M$ used in the second stage alleviates the speed constraints of the DT ${\Sigma\Delta}M$, whereas enables better matching between the analog and digital filter coefficients compared to CT ${\Sigma\Delta}Ms$.

A Low-Power CMOS Continuous-Time Sigma-Delta Modulator for UMTS Receivers (UMTS용 수신기를 위한 저 전력 CMOS 연속-시간 시그마-델타 모듈레이터)

  • Lim, Jin-Up;Choi, Joong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.8
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    • pp.65-73
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    • 2007
  • This paper presents a low power CMOS continuous-time $\Sigma\Delta$ (sigma-delta) modulator for UMTS receivers. The loop filter of the continuous-time $\Sigma\Delta$ modulator consists of an active-RC filter which performs high linearity characteristics and has a simple tuning circuit for low power operating system The architecture of this modulator is the $3^{rd}-order$ 4-bit single loop configuration with a 24 of OSR (Oversampling Ratio) to increase the power efficiency. The modulator includes a half delay feedback path to compensate the excess loop delay. The experimental results of the modulator are 71dB, 65dB and 74dB of the peak SNR, peak SMR and dynamic range, respectively. The continuous-time $\Sigma\Delta$ modulator is fabricated in a 0.18-um 1P4M CMOS standard process and dissipates 15mW for a single supply voltage of 1.8V.

CMOS Interface Circuit for MEMS Acceleration Sensor (MEMS 가속도센서를 위한 CMOS 인터페이스 회로)

  • Jeong, Jae-hwan;Kim, Ji-yong;Jang, Jeong-eun;Shin, Hee-chan;Yu, Chong-gun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.221-224
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    • 2012
  • This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

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New Gain Optimization Method for Sigma-Delta A/D Convertors (Sigma-Delta A/D 변환기의 새로운 이득 최적화 방식)

  • Jung, Yo-Sung;Jang, Young-Beom
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.9
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    • pp.31-38
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    • 2009
  • In this paper, we propose new gain optimization method for Sigma-Delta A/D converters. First, in proposed method, the 10 candidates are selected through SNR maximization for Sigma-Delta modulator. After then, it is shown that optimum gains can be obtained through MSE calculation for CIC decimation filter. In the simulation, The proposed method has advantages which utilize SNR maximization for modulator and MSE minimization for CIC decimation later. The more candidates are chosen in SNR maximization for modulator, the better gains can be obtained in MSE minimization for CIC decimation filter.

A 4th order SC Bandpass ${\sigma}-{\Delta}$ Modulator of Novel Architecture with Control of the Intermediate Frequency (중간주파수 조절이 가능한 새로운 구조의 4차 SC Bandpass ${\sigma}-{\Delta}$ Modulator)

  • Kim, Jae-Bung;Kim, Kang-Jik;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.3
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    • pp.31-35
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    • 2009
  • In this paper, tunable 4th order SC(switched capacitor) bandpass ${\sigma}-{\Delta}$(Sigma-Delta) modulator with advanced architecture that can adjust the IF by two coefficient values is proposed for data conversion in the wireless communication. Its architecture can optionally adjust all the 4th order noise transfer function in comparison with the conventional architecture. In order to adjust the IF, the conventional architecture needs the four variable coefficients values, basic clocks and eight clocks. On the other hand, the proposed architecture can adjust the IF by two variable coefficient values and basic clocks only.

A Tunable Bandpass $\Sigma-\Delta$ Modulator with Novel Architecture (새로운 구조를 가지는 Tunable Bandpass $\Sigma-\Delta$ Modulator)

  • Kim, Jae-Bung;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.135-139
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    • 2008
  • In this paper, tunable SC(switched capacitor) 2nd order bandpass $\Sigma-\Delta$(Sigma-Delta) modulator with novel architecture that can adjust the IF band center frequency by one coefficient value is proposed for data conversion in the IF(Intermediate Frequency) band. Its architecture can optionally adjust all the 2nd order noise transfer function in comparison with the conventional architecture. In order to adjust the center frequency, the conventional architecture needs the two variable coefficient values, basic clock and eight clocks. On the other hand, the proposed architecture can adjust the center frequency by one variable coefficient value and basic clock only.

A 1.2-V 0.18-${\mu}m$ Sigma-Delta A/D Converter for 3G wireless Applications

  • Kim, Hyun-Joong;Jung, Tae-Sung;Yoo, Chang-sik
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.627-628
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    • 2006
  • A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

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Improved Sigma Delta Modualtor Based On LMS Algorithm (LMS 알고리즘을 이용한 Sigma Delta Modulator)

  • 신원화;한건희;강성호;이철희
    • Proceedings of the IEEK Conference
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    • 2000.06e
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    • pp.81-84
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    • 2000
  • This paper proposes a new sigma delta modulator structure based on a LMS(Least Mean Square) algorithm that minimizes the quantization noise. The proposed architecture provides 40dB SNR improvement and 35dB wider dynamic range over conventional sigma delta modulation. The proposed architecture provides superior performance especially when the input signal is small.

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An Electromechanical ${\sum}{\triangle}$ Modulator for MEMS Gyroscope

  • Chang, Byung-Su;Sung, Woon-Tahk;Lee, Jang-Gyu;Kang, Tea-Sam
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.1701-1705
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    • 2004
  • This paper presents a design and analysis of electromechanical sigma-delta modulator for MEMS gyroscope, which enables us to control the proof mass and to obtain an exact digital output without additional A/D conversion. The system structure and the circuit realization of the sigma-delta modulation are simpler than those of the analog sensing and feedback circuit. Based on the electrical sigma-delta modulator theory, a compensator is designed to improve the closed loop resolution of the sensor. With the designed compensator, we could obtain enhanced closed-loop performances of the gyroscope such as larger bandwidth, lower noise, and digital output comparing with the results of analog open-loop system.

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