References
- S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, New York, 1996
-
L. J. Breems, R. Rutten, and G. Wetzker, 'A cascaded continuous-time
$\Sigma\Delta$ modulator with 67-dB dynamic range in 10-MHz bandwidth,' IEEE J. Solid State Circuits Vol.39, pp.2152-2160, Dec., 2004 https://doi.org/10.1109/JSSC.2004.836245 -
W. Redman-White, A. M. Durham, "Integrated fourth-order
$\Sigma\Delta$ converter with stable self-tuning continuous-time noise shaper," IEE Proc.-Circuits, Vol.141, pp.145-150, June, 1994 https://doi.org/10.1049/ip-cds:19949568 - L. Quiquerez, A. Kaiser, and D. Billet, 'A 112dB sigma-delta converter with a mixed continuous time/sample data architecture," Southwest Symposium on Mixed Signal Design. April 1999, pp.52-57 https://doi.org/10.1109/SSMSD.1999.768590
- K. Nguyen, R. Adams, K. Sweetland, and C. Huaijin, "A 106-dB SNR hybrid oversampling analog-todigital converter for digital audio," IEEE J. Solid State Circuits Vol.40, pp.2408-2415, Dec., 2005 https://doi.org/10.1109/JSSC.2005.856284
- M. Maghami and M. Yavari, "Multirate doublesampling hybrid CT/DT sigma-delta modulator for wideband applications," IEEE Int. Symposium on Circuits and Systems, May 2009, pp.2253-2256 https://doi.org/10.1109/ISCAS.2009.5118247
- P. Vaidyanathan, "Multirate digital filters, filter banks, poly-phase networks, and applications: a tutorial," IEEE Proc. Vol.78, pp.56-93, Jan., 1990 https://doi.org/10.1109/5.52200
-
K. S. Lee, S. Kwon, and F. Maloberti, "A power efficient time-interleaved
$\Sigma\Delta$ modulator for broadband applications," IEEE J. Solid State Circuits Vol.42, pp.1206-1215, June 2007 https://doi.org/10.1109/JSSC.2007.897151 - J. A. Cherry and W. M. Snelgrove, "Clock jitter and quantizer metastability in continuous-time delta-sigma modulators," IEEE Trans. Circ. Syst. II , pp.661-676, June 1999 https://doi.org/10.1109/82.769775
- Y. Chang, C. Lin, W. Wang, C. Lee, and C. Shih, "An analytical approach for quantifying clock jitter effects in continuouos-time sigma-delta modulators," IEEE Trans. Circ. Syst. I , pp.1861-1868, Sep., 2006 https://doi.org/10.1109/TCSI.2006.880035
- J. A. Cherry and W. M. Snelgrove, "Excess loop delay in continuous-time delta-sigma modulators," IEEE Trans. Circ. Syst. II , pp.376-389, April 1999 https://doi.org/10.1109/82.755409
- P. Benabes, M. Keramat, and R. Kielbasa, "A methodology for designing continuous-time deltasigma modulators," IEEE European Design and Test Conf., 1997, pp.46-50
- S. Yan and E. Sanchez, "A continuous-time sigmadelta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth," IEEE J. Solid State Circuits Vol.39, pp.75-86, Jan., 2004 https://doi.org/10.1109/JSSC.2003.820856
- Simulink and Matlab Users Guide, The Math Works, Inc., Natick, MA, 1997
-
T. C. Caldwell and D. A. Johns, "A time-interleaved continuous-time
$\Sigma\Delta$ modulator with 20- MHz signal bandwidth," IEEE J. Solid State Circuits Vol.41, pp.1578-1588, July 2006 https://doi.org/10.1109/JSSC.2006.873889 -
G. Mitteregger, C. Ebner, S. Mechnig, S. Blon, T. Holuigue, and E. Romani, 'A 20mW 640MHz CMOS continuous-time
$\Sigma\Delta$ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,' IEEE J. Solid State Circuits Vol.41, pp. 2641-2649, Dec., 2006 https://doi.org/10.1109/JSSC.2006.884332
Cited by
- A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators vol.78, pp.2, 2014, https://doi.org/10.1007/s10470-013-0232-6
- Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators vol.16, pp.3, 2016, https://doi.org/10.5573/JSTS.2016.16.3.319