• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1867-1875
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• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.4
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• pp.437-446
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• 2018

This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{\mu}s$ with a vector of length 48 with 2 non-zero elements.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.768-770
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• 2014

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of multiplication server farms. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• Journal of the Korean Mathematical Society
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• v.56 no.2
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• pp.523-537
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• 2019

We estimate the essential norms of Volterra-type integral operators $V_g$ and $I_g$, and multiplication operators $M_g$ with holomorphic symbols g on a large class of generalized Fock spaces on the complex plane ${\mathbb{C}}$. The weights defining these spaces are radial and subjected to a mild smoothness conditions. In addition, we assume that the weights decay faster than the classical Gaussian weight. Our main result estimates the essential norms of $V_g$ in terms of an asymptotic upper bound of a quantity involving the inducing symbol g and the weight function, while the essential norms of $M_g$ and $I_g$ are shown to be comparable to their operator norms. As a means to prove our main results, we first characterized the compact composition operators acting on the spaces which is interest of its own.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• Journal of the Korean Mathematical Society
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• v.55 no.1
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• pp.131-146
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• 2018

We generate ring class fields of imaginary quadratic fields in terms of the special values of certain eta-quotients, which are related to the relative norms of Siegel-Ramachandra invariants. These give us minimal polynomials with relatively small coefficients from which we are able to solve certain quadratic Diophantine equations concerning non-convenient numbers.

• Journal of the Korean Mathematical Society
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• v.52 no.5
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• pp.907-928
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• 2015

We show in many cases that the Siegel-Ramachandra invariants generate the ray class fields over imaginary quadratic fields. As its application we revisit the class number one problem done by Heegner and Stark, and present a new proof by making use of inequality argument together with Shimura's reciprocity law.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.173-176
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• 2000

This paper presents the development of an 8051-compatible microcontroller. The 8051 microcontroller is one the most popular mjcrocontroller used nowadays. All the features of the 8051, including peripherals, are implemented. The output of this work is a synthesizable RTL model that is readily available for a simple control unit in a more complex chip, such as an SOC. We put some important notes relating to the implementation of the 8051's features, including bit addressing, multiplication/division, etc.

• Journal of the Korean Mathematical Society
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• v.33 no.1
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• pp.205-216
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• 1996

In [13], Ptak and Vrbova proved that if T is a bounded normal operator T on a complex Hilbert space H, then the ranges of the spectral projections can be represented in the form $$ \varepsilon(F)H = \bigcap_{\lambda\notinF} (T - \lambda I) H for all closed subsets F of C, $$ where $\varepsilon$ denotes the spectral measure associated with T.

• Journal of the Korean Mathematical Society
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• v.50 no.4
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• pp.847-864
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• 2013

By a change of variables we obtain new $y$-coordinates of elliptic curves. Utilizing these $y$-coordinates as meromorphic modular functions, together with the elliptic modular function, we generate the fields of meromorphic modular functions. Furthermore, by means of the special values of the $y$-coordinates, we construct the ray class fields over imaginary quadratic fields as well as normal bases of these ray class fields.