• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.67-74
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• 2014

This paper presents a memristor-CMOS based RBSD adder. Conventional RBSD adders suffer bigger hardware due to the extra logic handling larger number of bits. The purpose of this paper is to improve the silicon surface area and the computation delay of conventional RBSD adders. The proposed method employs memristor-CMOS based circuit. The implementation results shows that the proposed memristor-CMOS based RBSD adder saves the cell area by 45%, and reduces time delay 24% compared to conventional RBSD adders. The proposed RBSD adder design can bring further area saving for large scale designs.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.8-14
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• 2008

A fully CMOS-integrated carbon nanotube (CNT) sensor array is proposed. After the sensor chip is fabricated in commercial CMOS process, the CNTs network is formed on the top of the fabricated sensor chip through the room-temperature post-CMOS processes. When the resistance of the CNT is changed by the chemical reaction, the read-out circuit in the chip measures the charging time of the $R_{CNT}$-Capacitor. finally the information of measured frequency is converted to a digital code. The CMOS sensor chip was fabricated by standard 0.18um technology and the size of the $8{\times}8$ sensor array is $2mm{\times}2mn$. We have carried out an experiment detecting the biochemical material, glutamate, using this sensor chip. From the experiment the CMOS sensor chip shows the feasibility of sensor for the simultaneous detection of the various target materials.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1108-1110
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• 1995

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.257-265
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• 2009

Recent progress in development of CMOS power amplifiers for mobile terminals is reviewed, focusing first on switching mode power amplifiers, which are used for transmitters with constant envelope modulation and polar transmitters. Then, various transmission line transformers are evaluated. Finally, linear power amplifiers, and linearization techniques, are discussed. Although CMOS devices are less linear than other devices, additional functions can be easily integrated with CMOS power amplifiersin the same IC. Therefore, CMOS power amplifiers are expected to have potential applications after various linearity and efficiency enhancement techniques are used.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.22-28
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• 1998

A $g_m$-control technique using a new electronic zener diode (EZD) for CMOS rail-torail input stages is presented. A regulated CMOS inverter is used as an EZD to obtain a constant-$g_m$ input stage. The turn-off characteristic of the proposed EZD is better than that of the existing EZD using two complementarey diodes, and thus, better $g_m$-control can be achieved. With this input stage, a 3V constant-$g_m$ rail-to-rail CMOS op-amp has been designed and fabricated using a $0.8\mu\extrm{m}$single-poly, double-metal CMOS process. Measurements results show that the $g_m$ variation is about 6% over the entire input common-mode range, and the op-amp has a dc gain of 88dB and a unity-gain frequency of 4MHz for $C_L=20pF, R_L=10k\Omega$

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.21-25
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• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.