• 대한전자공학회논문지
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• 제15권6호
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• pp.52-65
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• 1978

회로 해석 프로그램을 이용한 컴퓨터에 의한 칼라 TV 나로 설계를 시도하여 보았다. 칼라 TV의 colorplexed composite video signal은 여러가지 신호가 합쳐진 복합 신호이므로 칼라 TV 회로 설계를 하는 데에는 곤란한 점이 많다. 이 논문에서는 적절한 해석 프로그램을 선정하여 칼라 TV의 Y 영상회로, 색신호 증폭회로, AGC 회로 및 동기분리회로를 설계하는 방법을 기술하였다. 그리고 그 설계 방법이 타당함을 실험적으로 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1029-1032
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• 2000

A neuro-fuzzy based circuit to recognize circuit pat-terns is proposed in this paper. The simple algorithm and exemption from the use of template patterns as well as multipliers enable the proposed circuit to implement on the hardware of an economical scale. Furthermore, thanks to the circuit design by using current-mode techniques, the proposed circuit call achieve easy extendability of tile circuit and efficient pattern recognition with high-speed. The validity of the proposed algorithm and tile circuit design is confirmed by computer simulations. The proposed pattern recognition circuit is integrable by a standard CMOS technology.

• 한국정보통신학회논문지
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• 제17권9호
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• pp.2091-2096
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• 2013

본 논문에서는 방향성 그래프에 기초하여 절점들 간의 입출력 관계가 트리의 특성을 갖는 연관관계를 분할연산기법과 수학적 해석을 통하여 함수로 변환하고 이를 회로 설계하는 방법에 대하여 논의하였다. 기존에 제안된 알고리즘이 임의의 절점수를 갖는 방향성 그래프에 대하여 같은 수의 잉여절점수를 삽입함으로써 생성되는 매개변수들이 양의 정수로 표현되지 못하여 회로의 설계가 불가능하게 되는 문제점이 있었다. 이를 개선하기 위해서 본 논문에서는 트리의 성질을 수학적으로 해석하여 주어진 임의의 절점수를 가지는 방향성 그래프에 대하여 절점들의 관계를 규명해주는 매개변수들과 논리레벨 P의 승수로 표현되어 항상 양의 정수 값을 갖도록 레벨 간에 각기 다른 잉여절점을 삽입하여 효율적인 회로설계를 하였다.

• 한국정보통신학회논문지
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• 제7권4호
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• pp.798-804
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• 2003

본 논문에서는 프린터 head의 노즐분사제어를 위한 개선된 회로를 설계하였다. 기존 방식에 비하여 비하여 Pad 수를 줄임으로서 노즐 수를 확장시킬 수 있다. 제안된 회로는 사전검증을 위하여 먼저 20개의 노즐을 제어하는 sample 회로로 설계하고 FPGA를 이용하여 동작을 확인하였다. 320개의 노즐제어를 위한 전체회로는 sample 회로를 확장하여 ASIC Full Custom 설계방식을 통하여 설계한 뒤 로직 및 회로 simulation 검증을 하였다. 전체회로는 3$\mu\textrm{m}$ CMOS design rule을 적용하여 layout 및 chip으로 제작되었다.

• Journal of Power Electronics
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• 제7권4호
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• 전기의세계
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• 제28권9호
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• pp.51-59
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• 1979

The forming and design method of D.C thyristor chopper circuit for DC Series motor control is suggested, ard the computation method of thyristor commutaing element's, value which makes it all the more important, is possible. Also the trigger circuit was dealt with. In this paper, in order to control the duty cycle, the duty time is kept on constancy and variable chopping frequency was adopted. By above mentioned circuit design method, the D.C thyristor chopper circuit was implemented and tested. In this circuit, the result of D.C motor control was good and reliable. The relation between the $K_{d}$ and the ratio of input-output current, or the characteristic of speed was varied lineary at the range 0.1 ~ 0.9 of duty cycle. This confirms the fact that D.C to D.C power conversion which is the merit of chopper control is operated most likely a transformer.ormer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.521-522
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• 2006

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. The SIMULINK modeling was built in the frequency-time mixed domain whereas the Verilog-a modeling was built purely in the time domain. The simulated results of the two models were verified to show the same performance within the error tolerance. This top-down design method can provide the readiness for the transistor-level design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.523-524
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• 2006

Successive approximation A/D converters have an advantage of small chip area and simple algorithm. We propose an improved non-redundant successive approximation register (SAR) which can be incorporated in successive approximation A/D converters. The proposed SAR validates the preset state as the $1^{st}$ reference voltage to the comparator. Two redundant clock cycles in the typical design could be eliminated in the proposed A/D converter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• ETRI Journal
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• 제44권5호
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.