• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.424-428
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• 1987

A $2{\mu}m$ CMOS P-well double metal technology has been developed. Phosphorus deep implantation and drive-in diffusion steps were utilized to prevent the low voltage bulk punch through in the short channel, 1.6[${\mu}m$] Leff, PMOS device. Double metal process with the rules of 5[${\mu}m$] 1st metal pitch and 7[${\mu}m$] 2nd metal pitch was successfully implemented by using VLTO, low temperature oxide, as on intermetal dielectric.

• Journal of the Korean institute of surface engineering
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• v.33 no.4
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.40-45
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• 1991

It is well known that the conventional differential source-coupled pair uses gates as its input terminals. This input pair provids a high open-loop gain, a large CMRR, and a good PSRR. For these reasons, the input pair has been used widely as an input stages of the differential amplifiers, but a narrow linear input range of this structurelimits its application in the area of some analog circuit design. A novel CMOS source-coupled backgate pair is proposed in this paper. The bulk of MOSFET is exploited and input devices are biased to operate in ohmic region. With this topology, the backgate pair of the wide linear input range and variable transconductance can be obtained. This backgate input differential stage is realized with the size of W/L=50/25 MOSFETs. The results show the nonlinear error is less than $\gamma$1% over 10V full-scale range for the bias current of 200$\mu$A with 10V single power-supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.33-39
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• 2006

An empirical nonlinear model with intrinsic nonlinear elements has been newly developed to predict the RF nonlinear characteristics of nano-scale bulk MOSFET accurately over the wide bias range. Using an extraction method suitable for nano-scale MOSFET, the bias-dependent data of intrinsic model parameters have been accurately obtained from measured S-parameters. The intrinsic nonlinear capacitance and drain current equations have been empirically obtained through 3-dimensional curve-fitting to their bias-dependent curves. The modeled S-parameters of 60nm MOSFET have good agreements with measured ones up to 20GHz in the wide bias range, verifying the accuracy of the nano-scale MOSFET model.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.28-36
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• 2008

This paper discusses theimplementation of the low-voltage, low-power, third-order, 1-bit switched capacitor delta-sigma modulator of the implantable cardiac pacemaker. The distributed, feed-forward structure and bulk-driven OTA were used in order to achieve an efficient operation under a supply voltage of 1V or lower. The designed modulator has a dynamic range of 49dB at 0.9V supply voltage and consumes 816nW of power. Such a significant reduction in power consumption allows diverse applications, not only in pacemakers, but also in implantable biomedical devices that operate with limited battery power. The core chip size of the modulator is $1000{\mu}m*500{\mu}m$ manufactured, with the $0.18{\mu}m$ CMOS standard process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.