• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.812-822
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• 1997

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

• Journal of Internet Computing and Services
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• v.3 no.6
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• pp.1-11
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• 2002

The purpose of this paper is the design and implementation of asynchronous remote procedure call (RPC) resource service system using the XML technology. For this purpose, the request information of client is encoded into XML document based on XML-DOM and transferred to server, Server classifies the client requests into general application program and XML-RPC service using the object which can deal with the XML-DOM. In addition, server saves the request result of client in XML-DOM structure not transmitting it immediately in order to support asynchronous service, and makes the client request redirected to another request server in XML-DOM information. As a result, general RPC and XML-RPC services were attained and client request was redirected to servers, and the execution environment was simplified compared to common RPC.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.57-64
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• 2004

In this paper, we propose a RZ/HRZ mixture data transmission method for the asynchronous circuit design to reduce Power consumption. The dual-rail data with Rf decoding scheme is used to design asynchronous circuit, and it is easy to get a completion signal of the data validity from the native data as contrasted with sin91e-rail. However, the dual-rail scheme suffers from large chip area and increasing of Power consumption from all signals by the switching of the return-to-zero. We need to diminish number of circuit switching. The proposed RZ/HRZ data transmission reduces a switching activity to about 50% and it shows 23% lower power consumption than the conventional dual-rail coding with RZ's.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.173-181
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• 2014

This paper addresses the problem of model matching control for a class of systems modeled as input/output asynchronous sequential machines. Based on the feedback control scheme, we design a corrective controller that compensates the behavior of the closed-loop system so as to match a reference model. Whereas the former studies use state observers and the output burst for designing a controller, the present research needs neither the observer nor the output burst in controller design. We define the 'output equivalent machine' of the considered machine to describe the existence condition and the construction algorithm for the proposed controller. A case study is provided to show the operation of the proposed corrective controller.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.1-7
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• 2015

Until now, face to face coaching has been applied almost for completing the goal in various field. Face to face coaching is difficult always to reach each other anywhere, anytime due to the availability of internet and mobile devices. Recently, e-coaching is attempted to expend. But current e-coaching is supporting the secondary role for face to face coaching. E-coaching system has many benefits to use advancement technologies in internet. Therefore, the development of e-coaching system based on horizontal relationships between coach and coachee needs to communication anytime and anywhere in Internet. Usually previous online coaching systems have four types of interactions i.e. electronic mail, video chat, text chat, phone call. Most of the e-coaching approaches are easy to access and provide communication synchronous; video chat is an excellent visibility, whereas e-mail is asynchronous and document-centric. In this paper, we design and implement the integration e-coaching system based on synchronous and asynchronous. This system provides the asynchronous coaching offered by way of e-mail, and the synchronous coaching used P2P (Peer to Peer) video chat and text group chat. This system allows simultaneously asynchronous and synchronous coaching, and supports individual and group communication for periodical or informal coaching.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.4
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• pp.7-14
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• 2010

Stable-state behaviors of asynchronous sequential machines represented as finite state machines can be corrected by feedback control schemes. In this paper, we propose a state feedback control scheme for input/state asynchronous machines with uncertain transitions. The considered asynchronous machine is deterministic, but its state transition function is partially known due to model uncertainty or inner logic errors. The control objective is to compensate the behavior of the closed-loop system so that it matches a sub-behavior of a prescribed model despite uncertain transitions. Furthermore, during the execution of corrective action, the controller reflects the exact knowledge of transitions into the next step, i.e., the range of the behavior of the closed-loop system can be enlarged through learning. The design procedure for the proposed controller is described in a case study.