The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design and Performance Analysis of an Asynchronous Shared-Bus Type Switch with Priority and Fairness Schemes

  • Goo
  • Published : 1997.04.01
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Abstract

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

Keywords

References

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