1 |
M. Krstic, E. Grass, F. K. Gurkaynak, and P. Vivet, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook," IEEE Design & Test of Computers, vol. 24, no. 5, pp. 430-441, Sept.-Oct. 2007.
DOI
|
2 |
S. Hauck, "Asynchronous Design Methodologies : An Overview," Proceedings of the IEEE, vol. 83, no. 1, pp. 69-93, Jan. 1995.
DOI
|
3 |
A. Lines, "Asynchronous interconnect for synchronous SoC design," IEEE Micro, vol. 24, no. 1, pp. 32-41, Jan.-Feb. 2004.
DOI
|
4 |
"International Technology Roadmap for Semiconductors," Semiconductor Industry Association, 2012.
|
5 |
IBM Research, Introducing a Brain-Inspired Computer. (2014) [Online]. Available: http://www.research.ibm.com/articles/brain-chip.shtml.
|
6 |
M. Imai and T. Yoneda, "Improving Dependability and Performance of Fully Asynchronous On-chip Networks," in Proceeding of IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 65-76, Apr. 2011.
|
7 |
O. Naoya, A. Matsumoto, T. Funazaki and T.Hanyu, "High-Throughput Compact Delay-Insensitive Asynchronous NoC Router," IEEE Transactions on Computers, vol. 63, no. 3, pp. 637-649, Mar. 2014.
DOI
|
8 |
J. You, D. Gebhardt, and K. S. Stevens, "Bandwidth Optimization in Asynchronous NoCs by Customizing Link Wire Length," in Proceeding of IEEE International Conferfence on Computer Design (ICCD), pp. 455-461, Oct. 2010.
|
9 |
Y. Bei, C. Song, S. Dong, S. Chen, and S. Goto, "Floorplanning and Topology Generation for Application-Specific Network-on-Chip," in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 535-540, Jan. 2010.
|
10 |
D. Gebhardt, J. You, and K. S. Stevens, "Design of Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 9, pp. 1387-1399, Sept. 2011.
DOI
|
11 |
S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning : Enabling Hierarchical Design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6 pp. 1120-1135, Dec. 2003.
DOI
|
12 |
D. Gebhardt, J. You, and K. S. Stevens, "Link pipelining strategies for an application-specific asynchronous NoC," in Proceedings of IEEE/ACM International Symposium on Networks on Chip (NoCS), pp. 185-192, May. 2011.
|
13 |
Z. Wang, J. Xu, X. Wu, Y. Ye, W. Zhang, M. Nikdast, X. Wang. and Z. Wang, "Floorplan Optimization of Fat-Tree-Based Networks-onChip for Chip Multiprocessors," IEEE Transactions on Computers, vol. 63, no. 6, pp. 1446-1459, Jun. 2014.
DOI
|
14 |
D. Rostislav, V. Vishnyakov, E. Friedman and R. Ginosar, "An Asynchronous Router for Multiple Service Levels Networks on Chip," in Proceedings of IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 44-53, Mar. 2005.
|
15 |
J. J. H. Pontes, M. T. Moreira, F. G. Moraes, and N. L. V. Calazans, "Hermes-AA: A 65nm asynchronous NoC router with adaptive routing," in Proceedings of IEEE International SOC Conference (SOCC), pp. 493-498, Sept. 2010.
|
16 |
M. E. Dean, T. E. Williams, and D. L. Dill, "Efficient Selftiming with Level Encoded 2-phase Dual-rail (LEDR)," in Proceedings of University of California/Santa Cruz Conference on Advanced research in VLSI, pp. 55-70, Apr. 1991.
|
17 |
Y. Ar, S. Tosun, and H. Kaplan, "TopGen: A new algorithm for automatic topology generation for Network on Chip architectures to reduce power consumption," in Proceedings of International Conference on Application of Information and Communication Technologies (AICT), pp. 1-5, Oct. 2009.
|
18 |
D. Bertsimas and J. Tsitsiklis, "Simulated annealing," Statistical Science, vol. 8, no. 1, pp. 10-15, Feb. 1993.
DOI
|
19 |
Silicon Integration Initiative. Nangate open cell library. (2008) [Online], Avaialable: http://www.si2. org/openeda.si2.org/projects/nangatelib, Accessed on: May 2016.
|
20 |
R. P. Dick, D. L. Rhodes, and W. Wolf, "TGFF: Task Graphs for Free," in Proceedings of International Workshop on Hardware/Software Codesign (CODES/CASHE), pp. 97-101, Mar. 1998.
|