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http://dx.doi.org/10.5573/ieie.2016.53.8.049

Link-wirelength-aware Topology Generation for High Performance Asynchronous NoC Design  

Kim, Sang Heon (College of Information & Communication Engineering, Sungkyunkwan University)
Lee, Jae Sung (College of Information & Communication Engineering, Sungkyunkwan University)
Lee, Jae Hoon (College of Information & Communication Engineering, Sungkyunkwan University)
Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.8, 2016 , pp. 49-58 More about this Journal
Abstract
In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.
Keywords
Asynchronous Network-on-Chip (NoC); Topology generation; High performance design;
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