1 |
S. Hauck, 'Asynchronous design methodologies: an overview,' Proc. the IEEE, vol. 83, no. 1, pp. 69 - 93, Jan. 1995
DOI
ScienceOn
|
2 |
V. Akella, N. H. Vaidya, G. R. Redinbo, 'Limitations of VLSI implementations of delay-insensitive codes,' IEEE Proc.26th Int. Symp. on Fault-Tolerant Computing, pp. 208-217, Jun 1996
DOI
|
3 |
T. Verhoeff, 'Delay-insensitive code an overview,' Distributed Computing, vol. 3, pp. 1-8, 1988
DOI
|
4 |
W.J. Bainbridge, et. al. 'Delay-Insensitive, Point-to-Point Interconnect using m-of-n Codes', ASYNC' 2003, Vancouver, Canada, pp. 132-140, May 2003
DOI
|
5 |
W. J. Bainbridge, and S. B. Furber, 'Delay insensitive system-on-chip interconnect using 1-of-4 data encoding' Async' 2001, pp. 118-126, April 2001
DOI
|
6 |
D. W. Lloyd, and J. D. Garside, 'A practical comparison of asynchronous design styles', Async'2001, pp. 36-45, April 2001
DOI
|