Browse > Article

Adaptive Pipeline Architecture for an Asynchronous Embedded Processor  

Lee, Seung-Sook (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
Lee, Je-Hoon (CBNU BK21 Chungbuk Information Technology Center, Chungbuk National University)
Lim, Young-Il (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
Cho, Kyoung-Rok (Dept. of Computer and Communication Engineering and Research Institute for Computer and Information Communication, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.1, 2007 , pp. 51-58 More about this Journal
Abstract
This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design
Keywords
Asynchronous processor architecture; Asynchronous pipeline; Multi-processing;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S. Segars, 'The ARM9 family-high performance microprocessors for embedded applications,' Proc. ICCD, pp. 230 - 235, Oct. 1998   DOI
2 D. Sima, T. Fountain, and P. Kacsuk, Advanced Computer Architectures: a Design Space Approach, Addition-Wesley, 1997
3 J. L. Peterson, Petri nets theory and the modeling of systems, Englewood Cliffs, Prentice Hall 1981
4 J. D. Garside, W. J. Bainbridge, A. Bardsley, D. M. Clark, D. A. Edwards, S. B. Furber, J. Liu, D. W. Lloyd, S. Mohammadi, J. S. Pepper, O. Petlin, S. Temple, J. V. Woods, 'AMULET3i-an asynchronous system-on-chip,' Proc. ASYNC2000, pp. 162-175, Apr. 2000   DOI
5 A. Efthymiou and J. D. Garside, 'Adaptive pipeline structures for speculation control,' Proc. ASYNC'03, pp. 46-55, May 2003   DOI
6 J. L. Peterson, 'Petri nets,' ACM Computing surveys, vol. 9, no. 3, sept. 1977
7 J. M. Colmenar, O. Garnica, S. Lopez, J. I. Hidalgo, J. Lanchares, and R. Hermida, 'Empirical characterization of the latency of long asynchronous pipelines with data-dependent module delays,' Proc. 12th EUROMICROPDP' 04, pp. 311-321, Feb. 2004   DOI
8 A. J. Martin, M. Nystrom, K. Papadantonakis, P. I. Penzes, P. Prakash, C. G. Wong, J. Chang, K. S. Ko, B. Lee, E. Ou, J. Pugh, E. Talvala, J. T. Tong, and A. Tura, 'The lutonium subnanojoule asynchronous 8051 microcontroller,' Proc ASYNC'03, pp. 14-23, 2003
9 J. H. Lee, Y. H. Kim, and K. R. Cho, 'Design of a fast asynchronous embedded CISC microprocessor, A8051,' IEICE Trans. on Electron, vol. E87-C, no. 4, pp. 527-534. Apr. 2004
10 S. B. Furber, J. D. Garside, S. Temple, J. Liu, P. Day, and N. C. Paver, 'AMULET2e An asynchronous embedded controller,' Proc ASYNC'1997, pp. 290-299, Apr. 1997   DOI
11 A. Takamura, M, Kuwakao, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno, and T. Nanya, 'TITAC-2 A 32-bit scalable-delay insensitive microprocessor,' Proc. ICCD, pp. 288-294, Oct. 1997
12 S. B. Furber, D. A. Edward, and J. D. Garside, 'AMULET3: A 100 MIPS asynchronous embedded processor,' Proc. Computer Design, pp. 329-334, 2000   DOI
13 M. Ozawa, M. Imai, Y. Ueno, H. Nakamura, and T. Nanya, 'A cascade ALU architecture for asynchronous super-scalar processor,' IEICE Trans. Electron., vol. E84-C, no. 2, pp. 229-237, Feb. 2001