• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1965-1970
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• 2011

This paper proposes the method of switching function implementation using switching function extraction based on graph over finite fields. After we deduce the matrix equation from path number of directional graph, we propose the switching function circuit algorithm, also we propose the code assignment algorithm for nodes which is satisfied the directional graph characteristics with designed circuits. We can implement more optimal switching function compare with former algorithm, also we can design the switching function circuit which have any natural number path through the proposed switching function circuit implementation algorithms. Also the proposed switching function implementation using graph theory over finite fields have decrement number of input-output, circuit construction simplification, increment arithmetic speed and decrement cost etc.

• Progress in Superconductivity
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• v.5 no.1
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.141-143
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• 2002

We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.661-663
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• 2002

현대의 Deep-Submicron Technology(DSM)에선 배선에 관련된 문제, 예를 들어 crosstalk이나 노이즈 등이 큰 문제가 된다. 그리하여, 배선은 논리 구성요소들보다 더욱 중요한 위치를 차지하게 되었다. 우리는 이러한 배선을 고려하여 연산식을 최적화하기 위해 carry-save-adder(CSA)를 이용한 모듈 함성 알고리즘을 제시한다. 즉, 상위 단계에서 생성 된 규칙적인 배선 토폴로지를 유지하며 CSA간의 배선을 좀더 향상시키는 최적의 알고리즘을 제안한다. 우리는 우리의 이러한 방법으로 생성된 지연시간이 [1]에 가깝거나 거의 근접하는 것을 많은 testcase에서 보이며(배선을 포함하지 않은 상태에서), 그리고 그와 동시에 최종 배선의 길이가 짧고 규칙적인 구조를 갖는것을 보인다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.157-160
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• 2002

This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.195-198
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• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.4
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• pp.533-542
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• 1994

This paper presents the new algorithm for fault analysis and this algorithm obtains requisite term for fault analysis by the two-port network technique. Therefore, the fault calculation time is composed of only few fundamental arithmetic calculation. The graphic user environment for fault analysis is implemented in mouse-oriented user interface with window and pull-down menu. The result of the algorithm proved to be identical with the sample system in Ref.[8]. this package can be a useful tool for fault analysis.