비동기회로 합성을 위한 병행 프로그램의 페트리 넷으로의 변환

Translating concurrent programs into petri nets for synthesis of asynchronous circuits

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.