• Title/Summary/Keyword: annealing process

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1.5 kV GaN Schottky Barrier Diode for Next-Generation Power Switches (차세대 전력 스위치용 1.5 kV급 GaN 쇼트키 장벽 다이오드)

  • Ha, Min-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.11
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    • pp.1646-1649
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    • 2012
  • The $O_2$ annealing technique has considerably suppressed the leakage current of GaN power devices, but this forms NiO at Ni-based Schottky contact with increasing on-resistance. The purpose of the present study was to fabricate 1.5 kV GaN Schottky barrier diodes by improving $O_2$-annealing process and GaN buffer. The proposed $O_2$ annealing performed after alloying ohmic contacts in order to avoid NiO construction. The ohmic contact resistance ($R_C$) was degraded from 0.43 to $3.42{\Omega}-mm$ after $O_2$ annealing at $800^{\circ}C$. We can decrease RC by lowering temperature of $O_2$ annealing. The isolation resistance of test structure which indicated the surface and buffer leakage current was significantly increased from $2.43{\times}10^7$ to $1.32{\times}10^{13}{\Omega}$ due to $O_2$ annealing. The improvement of isolation resistance can be caused by formation of group-III oxides on the surface. The leakage current of GaN Schottky barrier diode was also suppressed from $2.38{\times}10^{-5}$ to $1.68{\times}10^{-7}$ A/mm at -100 V by $O_2$ annealing. The GaN Schottky barrier diodes achieved the high breakdown voltage of 700, 1400, and 1530 V at the anode-cathode distance of 5, 10, and $20{\mu}m$, respectively. The optimized $O_2$ annealing and $4{\mu}m$-thick C-doped GaN buffer obtained the high breakdown voltage at short drift length. The proposed $O_2$ annealing is suitable for next-generation GaN power switches due to the simple process and the low the leakage current.

The Changes of Short Circuit Current Density according to the Post-annealing Temperature of Organic Materials in the Hybrid Photovoltaics (하이브리드 태양전지 제작에 있어서 유기물의 후열처리 온도에 따른 단락전류밀도의 변화)

  • Gwon, Dong-Oh;Shin, Min Jeong;Ahn, Hyung Soo;Yi, Sam Nyung
    • Journal of Advanced Marine Engineering and Technology
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    • v.39 no.1
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    • pp.81-85
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    • 2015
  • The organic/inorganic hybrid photovoltaic devices have been studied using Poly(3-hexylthiophene-2,5-diyl) (P3HT) : [6, 6]-Phenyl C61 butyric acid methyl ester (PCBM) and GaN. We traced the effect of short circuit current density with different annealing method under the various concentration and ratio of P3HT:PCBM. During the pre-annealing course, the heat treatments were performed each time at low temperature after the organic layer coated and the samples were heated at high temperature through one or two steps under the post-annealing process. It revealed that the samples with post-annealing process had higher values of short circuit current density than the other samples upon pre-annealing. And the interesting high short circuit current density features were observed at 1:1 mixing ratio and 1wt% of P3HT:PCBM.

Physical Property Change of the Gapless Semiconductor $PbPdO_2$ Thin Film by Ex-situ Annealing

  • Choo, S.M.;Park, S.M.;Lee, K.J.;Jo, Y.H.;Park, G.S.;Jung, M.H.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.371-372
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    • 2012
  • We have studied lead-based gapless semiconductors, $PbPdO_2$, which is very sensitive to external parameters such as temperature, pressure, electric field, etc[1]. We have fabricated pure $PbPdO_2$, Co- and Mn-doped $PbPdO_2$ thin films using the pulsed laser deposition. Because of the volatile element of Pb, it is very difficult to grow the films. Note that in case of $MgB_2$, Mg is also volatile element. So in order to enhance the quality of $MgB_2$, some experiments are carried out in annealing with Mg-rich atmosphere [2]. This annealing process with volatile element plays an important role in making smooth surface. Thus, we applied such process to our studies of $PbPdO_2$ thin films. As a result, we found the optimal condition of ex-situ annealing temperature ${\sim}650^{\circ}C$ and time ~12 hrs. The ex-situ annealing brought the extreme change of surface morphology of thin films. After ex-situ annealing with PbO-rich atmosphere, the grain size of thin film was almost 100 times enlarged for all the thin films and also the PbO impurity phase was smeared out. And from X-ray diffraction measurements, we determined highly crystallized phases after annealing. So, we measured electrical and magnetic properties. Because of reduced grain boundary, the resistivity of ex-situ annealed samples changed smaller than no ex-situ sample. And the carrier densities of thin films were decreased with ex-situ annealing time. In this case, oxygen vacancies were removed by ex-situ annealing. Furthermore, we will discuss the transport and magnetic properties in pure $PbPdO_2$, Co- and Mn-doped $PbPdO_2$ thin films in detail.

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Shallow Junction Device Formation and the Design of Boron Diffusion Simulator (박막 소자 개발과 보론 확산 시뮬레이터 설계)

  • Han, Myoung Seok;Park, Sung Jong;Kim, Jae Young
    • 대한공업교육학회지
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    • v.33 no.1
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    • pp.249-264
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    • 2008
  • In this dissertation, shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes and a new simulator is designed to model boron diffusion in silicon. This simulator predicts the boron distribution after ion implantation and annealing. The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a RTA(Rapid Thermal Annealing) and a FA(Furnace Annealing) process. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of sheet resistance and the simulator reproduced experimental data successfully. Therefore, proposed diffusion simulator and FA+RTA annealing method was able to applied to shallow junction formation for thermal budget. process.

A Study on the Formability of Autonobile Panel on the Heat Treatment Method (자동차용 강판의 소둔방법에 따른 성형성의 변화에 관한 연구)

  • 김순경;이승수;전언찬
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1995.10a
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    • pp.629-632
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    • 1995
  • The formability of an automobile body panel is very important. So, we performed an annealing condition change for the development of annealing condition with temperature, atmospheric gas and the annealing cycle. Formability was changed under the influenced of the mechanical properties of steel sheet for the automobile body panel. Therefore, ot os important in the BAF(Batch annealing furnace) annealing process. Because mechanical properties were decided on the heat treatment method of the coil. So, we tested the development of mechanical properties according to the heat treatment method at the annealing furnace using the Ax atmospheric gas and the HNx atmospheric gas. As a result of several investigations, we confirmed the following characteristics ; mechanical properties change under the influence of the annealing cycle and atmospheric gas.

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Analysis on the Optical Properties and Fabrication of Textured AZO Thin Films for Increasing the Efficiency of LED (LED 효율 향상을 위한 Texture구조 AZO 박막의 제조와 광학적 특성분석)

  • Kim Kyeong-Min;Jin Eun-Mi;Park Choon-Bae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.10
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    • pp.901-906
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    • 2006
  • The transparent conductive oxide(TCO) has been used in necessity as front electrode for increasing efficiency of LED. In our paper, aluminium-doped zinc oxide films(AZO), which has transparent conducting were prepared with RF magnetron sputtering system on glass substrate(corning 1737) and annealed at $400^{\circ}C$ for 2 hr in vacuum ambient and $600^{\circ}C$ for 2hr with $O_2$ ambient respectively. The smooth AZO films were etched in diluted HCL(0.5 %) to examine the surface properties, which in ambient post-annealing process. We confirmed that the electric, structural and optical properties of textured AZO thin films, which implemented using the methods of XRD, FWHM, AFM and Hall measurement. The properties of textured AZO thin films especially depended on the ambient post-annealing process. We presumed that the change of transmittances as R G B LED and the ambient post-annealing process will be increasing the efficiency of LED.

Microstructure and Electrical Properties of ZnO Thin Film for FBAR with Annealing Temperature (FBAR용 ZnO 박막의 열처리 온도변화에 따른 미세조직 및 전기적 특성)

  • Kim, Bong-Seok;Kang, Young-Hun;Cho, Yu-Hyuk;Kim, Eung-Kwon;Lee, Jong-Joo;Kim, Young-Sung
    • Journal of the Korean Ceramic Society
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    • v.43 no.1 s.284
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    • pp.42-47
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    • 2006
  • In this paper, we prepared high-quality ZnO thin films for application of FBAR (Film Bulk Acoustic Resonator) by using pulse DC magnetron sputtering. To prevent the formation of low dielectric layers between metal and piezoelectric layer, Ru film of 30 nm thickness was used as a buffer layer. In addition we investigated the influence of annealing condition with various temperatures. As the annealing temperature increased, the crystalline orientation with the preference of (002) c-axis and resistance properties improved. The single resonator which was fabricated at $500^{\circ}C$ exhibited the resonance frequency and the return loss 0.99 GHz and 15 dB, respectively. This work demonstrates potential feasibility for the use of thin film Ru buffer layers and the optimization of annealing condition.

The variation of C-V characteristics of thermal oxide grown on SiC wafer with the electrode formation condition (SiC 열산화막의 Electrode형성조건에 따른 C-V특성 변화)

  • Kang, M.J.;Bahng, W.;Song, G.H.;Kim, N.K.;Kim, S.C.;Seo, K.S.;Kim, H.W.;Kim, E.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.354-357
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    • 2002
  • Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

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Effects of Annealing on Solution Processed n-ZTO/p-SiC Heterojunction (용액 공정으로 형성된 n-ZTO/p-SiC 이종접합 열처리 효과)

  • Jeong, Young-Seok;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.28 no.8
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    • pp.481-485
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    • 2015
  • We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.

Void Defects in Composite Titanium Disilicide Process (복합 티타늄실리사이드 공정에서 발생한 공극 생성 연구)

  • Cheong, Seong-Hwee;Song, Oh-Sung
    • Korean Journal of Materials Research
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    • v.12 no.11
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    • pp.883-888
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    • 2002
  • We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.