• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.132-138
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• 2014

The use of AGVs(Automated Guided Vehicles) are increasing in many factories. The most widely used AGV system is that magnetic tapes are attached on the factory floor to make guided path and an AGV equipped with a magnetic sensor follows the path by sensing magnetic flux. In this AGV system, usually a magnetic sensor is attached on the front end of an AGV to detect the guided path and the sensor generates analog voltages proportional to the magnetic flux. The problem is that the AGV in use has rather big tracking errors because the accurate orientation of the AGV can not be detected by using only one magnetic sensor. In this paper, we propose a method to minimize the path tracking errors. In our method, one additional sensor is attached on the rear end of the AGV to estimate the orientation of the AGV and to control more accurately the AGV according to the estimated orientation of the AGV. We performed several experiments and the results successfully show the feasibility of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.462-468
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• 2012

In this paper, an adaptive digital automatic gain control(AGC) algorithm with two stages is proposed. AGC technique is crucial for mobile communication equipment because path loss in wireless channel and gain fluctuation in receiver front-end continuously change the received signal strength. Furthermore, adaptive criteria should be applied to the design of AGC algorithm in order to support many waveforms with one SDR communication device. With these reasons, a two-stage structure is proposed to satisfy both flexibility and adaptiveness. Compared with conventional method, it also requires shorter convergence time. Numerical results show that the gain value of variable gain amplifier(VGA) is converged within proper time and proposed scheme controls the input level of analog to digital converter(ADC) to be stable during long range of time.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1303-1310
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• 2016

In this paper, electrocardiogram (ECG) analog front end with supply voltage of 0.5V has been designed and verified by measurements of fabricated chip. ECG is composed of instrument amplifier, 6th order gm-C low pass filter and variable gain amplifier. The instrument amplifier is designed to have gain of 34.8dB and the 6th order gm-C low pass filter is designed to obtain the cutoff frequency of 400Hz. The operational transconductance amplifier of the low pass filter utilizes body-driven differential input stage for low voltage operation. The variable gain amplifier is designed to have gain of 6.1~26.4dB. The electrocardiogram analog front end are fabricated in TSMC $0.18{\mu}m$ CMOS process with chip size of $858{\mu}m{\times}580{\mu}m$. Measurements of the fabricated chip is done not to saturate the gain of ECG by changing the external resistor and measured gain of 28.7dB and cutoff frequency of 0.5 - 630Hz are obtained using the supply voltage of 0.5V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.200-220
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• 2016

Orthogonal frequency division multiplexing (OFDM) signals suffer from the problem of large peak-to-average power ratio (PAPR) which complicates the design of the analog front-end of the system. Companding is a well-known PAPR reduction technique that reduces the PAPR by transforming the signal amplitude using a deterministic function. In this paper, a novel piecewise linear companding transform is proposed. The design criteria for the proposed transform is developed by investigating the relationships between the compander and decompander's profile and parameters with the system's performance metrics. Using analysis and simulations, we relate the companding parameters with the bit error rate (BER), out-of-band interference (OBI), amount of companding noise, computational complexity and average power. Based on a set of criteria developed thereof, we formulate the design of the proposed transform. The main aim is to preserve the signal's attributes as much as possible for a predetermined amount of PAPR reduction. Simulations are carried out to evaluate and compare the proposed scheme with the existing companding transforms to demonstrate the enhancement in PAPR, BER and OBI performances.

• Journal of information and communication convergence engineering
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• v.13 no.4
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• pp.235-240
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• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1282-1287
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• 2002

In this Paper, we present the design of 10Mbps HomePNA(Home Phoneline Networking Alliance) PHY which is Home Network Technology using phone-line. It is connected with external interface through MII(Media Independent Interface) and AFE(Analog Front End) Interface. 10Mbps HomePNA PHY is composed with Management Block IEEE 802.3 CSMA/CD MAC(Media Access Control) Block Modulator block and Demodulator block. For their verification, we designed a prototype FPGA PCB board using XPC860T made in Motorola. We verified HomePNA frame data transmission using a driver program based Linux kernel. we verified rate negotiation by HomepNA 2.0 Link Layer Protocol.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1449-1454
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• 2012

Received signal strength indicator (RSSI) represents the strength of the received signal at the front end of analog-to-digital convertor (ADC) input. RSSI value can be used for deciding the status of channel at the receiver. In this paper, the usage of RSSI in handover is studied using the practical measurement data. We first measure RSSI in 5.9GHz frequency band which is commonly used in wireless access in vehicular environments (WAVE) system. i.e., vehicular communications. Then, to implement a fast handover, the usability of RSSI data is analyzed based on the measured data. We also apply handover in practical highway environments.