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A design of HomePNA2.0 PHY.  

박성희 (한국전자통신연구원 네트워크연구소 SoC기술팀)
구기종 (한국전자통신연구원 네트워크연구소 SoC기술팀)
김종원 (한국전자통신연구원 네트워크연구소 SoC기술팀)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.27, no.12C, 2002 , pp. 1282-1287 More about this Journal
Abstract
In this Paper, we present the design of 10Mbps HomePNA(Home Phoneline Networking Alliance) PHY which is Home Network Technology using phone-line. It is connected with external interface through MII(Media Independent Interface) and AFE(Analog Front End) Interface. 10Mbps HomePNA PHY is composed with Management Block IEEE 802.3 CSMA/CD MAC(Media Access Control) Block Modulator block and Demodulator block. For their verification, we designed a prototype FPGA PCB board using XPC860T made in Motorola. We verified HomePNA frame data transmission using a driver program based Linux kernel. we verified rate negotiation by HomepNA 2.0 Link Layer Protocol.
Keywords
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 22. Reconciliation Sublayer(RS) and Media Independent Interface(MII) /
[] / IEEE Std 802.3, Local and Metropolitan Area Networks
2 10Mbps급 HomePNA기술의 Frame Processor 구조 설계 /
[ 구기종;김종원 ] / 대한전자공학회 통신 소사이어티 및 신호처리 소사이어티 추계 합동 학술 발표회 논문집
3 HomePNA 기술 /
[ 김종원;양재우 ] / 한국통신학회지   과학기술학회마을
4 /
[ HomePNA ] / Interface Specification for HomePNA2.0 10M8 Technology
5 /
[] /
6 HomePNA1.0 Transceiver의 회로 설계 및 구현 /
[ 구기종;유광현;홍인성;김보관 ] / 대한전자공학회, 추계종합학술대회 논문집