• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.188-193
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• 2010

In this paper, SI(Signal Integrity) characteristic of the 4-layer PCB(Printed Circuit Boards) with a through-hole via was analyzed by impedance mismatching between the through-hole via and the transmission line, and deterioration of clock pulse response characteristic due to the P/G plane resonances which are generated between the power and the ground plane. The minimized impedance mismatching between the through-hole via and the transmission line for the improving of SI characteristic is confirmed by the TDR(Time Domain Reflector) simulation and lumped element modeling of the through-hole via. And the cancellation method of P/G plane resonances for improvement of the SI characteristic is represented by simulation result.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1972-1975
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• 2002

In this paper, we have proposed low temperature co-fired ceramic (LTCC) based packaging for RF MEMS devices. The packaging structure is designed and evaluated with 3D full field simulation. 50 ${\Omega}$ matched coplanar waveguide(CPW) transmission line is employed as the test vehicle to evaluate the performances of the proposed package structure. The line is encapsulated with the LTCC packaging lid and connected to the via feed line. To reduce the insertion loss due to the packaging lid, the cavity with via post is formed in the packaging lid. The performances of the package structure is simulated with the different cavity depth and via-to-via length. Simulation results show that the proposed package structure has reflection loss better than 20 dB and insertion loss lower than 0.1 dB from DC to 30 GHz with the cavity depth and via-to-via length of 300 ${\mu}m$ and 350 ${\mu}m$, respectively. To realize the designed package structure, the cavity patterning is tested using the sandblast of LTCC.

• Journal of the Korean institute of surface engineering
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• v.46 no.4
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• pp.153-157
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• 2013

The defect like the void or seam is frequently generated in the PCB (Printed Circuit Board) Via-Filling plating inside via hole. The organic additives including the accelerating agent, inhibitor, leveler, and etc. are needed for the copper Via-Filling plating without this defect for the plating bath. However, the decomposition of the organic additive reduces the lifetime of the plating bath during the plating process, or it becomes the factor reducing the reliability of the Via-Filling. In this paper, the interaction of each organic additives and the decomposition of additive were discussed. As to the accelerating agent, the bis (3-sulfopropyl) disulfide (SPS) and leveler the Janus Green B (JGB) and inhibitor used the polyethlylene glycol 8000 (PEG). The research on the interaction of the organic additives and decomposition implemented in the galvanostat method. The additive decomposition time was confirmed in the plating process from 0 Ah/l (AmpereHour/ liter) to 100 Ah/l with the potential change.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.244-250
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• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.234-239
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• 2011

In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.123-127
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• 2009

In order to get more higher integration density of devices, it is getting to be used more and more micro via interconnection lines for interconnecting layers or devices. However, it is very important to enhance the electrical characteristic by reducing the electrical resistivity of micro via interconnection line because it affects the reliability of packaging. In this paper, Micro vias were patterned with a diameter from 10 to 100 um by increasing the step of 10 um and 100 um height and were fabricated by micromachining technology to investigate the electrical characteristic of micro via interconnection lines. These micro vias were filled with copper by electroplating process with appling pulse current mode. And the electrical characteristics of micro via interconnection lines were measured. The measured value of electrical resistivity shows with a range from 20 to $26\;m{\Omega}$. This value from micro via interconnection lines fabricated by pulse current mode electroplating process shows better result than the resistivity from than micro via interconnection lines fabricated by DC mode ($31\;m{\Omega}$).

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.616-618
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• 2002

최근에는 고성능 네트웍으로 구성된 클러스터 상에서 사용자 수준 통신을 사용하는 소프트웨어 분산 공유메모리 시스템의 연구가 활발히 진행되고 있다. 본 논문에서는 사용자수준 프로토콜의 표준인 Virtual Interface Architecture(VIA)를 사용하고 확장성 있는 Home-based Lazy release Consistency(HLRC) 모델을 기반으로 하는 소프트웨어 분산공유메모리 시스템을 구현한다. 본 시스템은 VIA의 원격 메모리 쓰기 기능을 최대한 활용하며, 통신 과정에서 통신 버퍼와 사용자 메모리 사이의 복사가 일어나지 않도록 설계되어 높은 성능을 보인다.

• Bulletin of the Korean Mathematical Society
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• v.49 no.5
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• pp.939-947
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• 2012

In this paper, we give a generalization of the embeddings of Riemannian manifolds via their heat kernel and via a finite number of eigenfunctions. More precisely, we embed a family of Riemannian manifolds endowed with a time-dependent metric analytic in time into a Hilbert space via a finite number of eigenfunctions of the corresponding Laplacian. If furthermore the volume form on the manifold is constant with time, then we can construct an embedding with a complete eigenfunctions basis.