• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.287-294
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• 2011

In this paper, two competing mechanisms determining drain current of tunneling field-effect transistors (TFETs) have been investigated such as band-to-band tunneling and drift. Based on the results, the characteristics of TFETs have been discussed in the tunneling-dominant and drift-dominant region.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.611-613
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• 2016

TCAD 시뮬레이션을 이용하여 소스영역으로 오버랩된(overlapped) 게이트를 가진 터널링 전계효과 트랜지스터(Tunnel Field-Effect Transistor; TFET)의 오버랩된 게이트 길이에 따른 터널링 전류 특성을 조사하였다. 터널링은 크게 라인터널링과 포인트 터널링으로 구분되는데, 라인터널링이 포인트터널링보다 subthreshold swing(SS), on-current에서 더 높은 성능을 보인다. 본 논문은 Silicon, Germanium, Si-Ge Hetero TFET구조에서 게이트 길이를 소스영역으로 오버랩될 경우에 포인트 터널링과 라인터널링의 효과를 조사해서 SS와 on-current에 최적합한 구조의 가이드라인을 제시한다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2019년도 춘계학술대회
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• pp.475-476
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• 2019

L형 터널링 전계 효과 트랜지스터 (LTFET)는 종래의 터널링 전계 효과 트랜지스터 (TFET)보다 우수한 소자로 고려된다. 그러나, 실험적으로 입증 된 LTFET은 트랩 상태의 존재로 인한 트랩-보조-터널링 (Trap-Assisted-Tunneling; TAT)에 기인한 열악한 임계 이하 기울기(SS) 특성을 나타내었다. 본 논문에서는 실험적으로 시연 된 LTFET의 저전압 바이어스에 TAT 메커니즘을 밴드 다이어그램과 TAT 재조합률 (GTAT)을 사용하여 조사한다.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1481-1486
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• 2013

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.272-277
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• 2011

The ambipolar behavior of tunneling field-effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (${\nu}$). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ${\nu}$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.172-178
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• 2016

In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length ($L_{ch}$) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current ($I_{off}$) of $1.12{\times}10^{-11}A/{\mu}m$. In addition, the use of the highk spacer dielectric $HfO_2$ improves the on-state current ($I_{on}$) with an intrinsic delay time (${\tau}$) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower $I_{off}$ at a lower supply voltage ($V_{DD}$) of 0.2 V.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.170-171
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• 2016

A surface potential model is introduced for L-shaped tunnel field-effect-transistor(L-TFET). Excellent agreement is obtained when model results are compared with TCAD data.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.445-447
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• 2016

터널링 전계효과 트랜지스터(Tunneling Field-Effect Transistor; TFET) 중에 이중 게이트 TFT(DG-TFET)와 단일 게이트 TFET(SG-TFET)의 구조에 따른 성능 비교를 조사했다. 채널 길이가 30nm 이상, 실리콘 두께 20nm이하, 게이트 절연막 두께는 작아질수록 SG-TFET와 DG-TFET subthrreshold swing과 온 전류 성능이 향상됨을 보였다. 다양한 파라미터에서 DG-TFET의 성능이 SG-TFET 성능보다 향상됨을 보인다.