Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology
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Cho, Seong-Jae
(Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)
Sun, Min-Chul (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) Kim, Ga-Ram (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) Kamins, Theodore I. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) Park, Byung-Gook (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) Harris, James S. Jr. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) |
1 | M.-H. Juang, P.-S. Hu, and S.-L. Jang, "Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate," Semicond. Sci. Technol., Vol.24, No.2, pp.025019-1-025019-4, Feb., 2009. DOI ScienceOn |
2 |
G. B. Stringfellow, "Electron mobility in |
3 |
A. K. Saxena, "Electron mobility in |
4 | W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less than 60 mV/dec," IEEE Electron Device Lett., Vol.28, No.8, Aug., 2007. |
5 | J. Knoch and J. Appenzeller, "Modeling of High- Performance p-Type III-V Heterojunction Tunnel FETs," IEEE Electron Device Lett., Vol.31, No.4, Apr., 2010. |
6 | P.-F. Guo, L.-T. Yang, Y. Yang, L. Fan, G.-Q. Han, G. S. Samudra, and Y.-C. Yeo, "Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current," IEEE Electron Device Lett., Vol.30, No.9, Sep., 2009. |
7 | W. Y. Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide- Semiconductor Field-Effect Transistors," Jpn. J. Appl. Phys., Vol.49, No.4, pp.04DJ12-1-04DJ12-3, Apr., 2010. DOI |
8 | E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device Physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications," J. Appl. Phys., Vol.103, No.10, pp.104504-1-104504-5, May, 2008. DOI ScienceOn |
9 | K. Ganapathi and S. Salahuddin, "Heterojunctino Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High ON Current," IEEE Electron Device Lett., Vol.32, No.5, pp.689- 691, May, 2011. DOI |
10 | ATLAS User's Manual, Silvaco International, Santa Clara, CA, Nov/Dec., 2008. |
11 | Process Integration, Devices & Structures (PIDS), International Technology Roadmap for Semiconductors (ITRS), 2009 edition. |
12 | Y. Apanovich, P. Blakey, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and A. Tcherniaev, "Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects," IEEE Trans. Electron Devices, Vol.42, No.2, pp.890-898, May, 1995. DOI ScienceOn |
13 | O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of Tunneling Field-Effect Transistors Using Strained -Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol.29, No.9, pp.1074-1077, Sep., 2008. DOI ScienceOn |
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