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http://dx.doi.org/10.5573/JSTS.2011.11.3.182

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology  

Cho, Seong-Jae (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)
Sun, Min-Chul (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University)
Kim, Ga-Ram (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University)
Kamins, Theodore I. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)
Park, Byung-Gook (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)
Harris, James S. Jr. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.11, no.3, 2011 , pp. 182-189 More about this Journal
Abstract
In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).
Keywords
Tunneling field-effect transistor (TFET); Type-I heterojunction; narrow bandgap material; high mobility; simulation; nanowire; high performance (HP) logic technology;
Citations & Related Records

Times Cited By SCOPUS : 5
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1 M.-H. Juang, P.-S. Hu, and S.-L. Jang, "Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate," Semicond. Sci. Technol., Vol.24, No.2, pp.025019-1-025019-4, Feb., 2009.   DOI   ScienceOn
2 G. B. Stringfellow, "Electron mobility in $Al_{x}Ga_{1}-_{x}As$," J. Appl. Phys., Vol.50, No.6, pp.4178-4183, Jun., 1979.   DOI   ScienceOn
3 A. K. Saxena, "Electron mobility in $Ga_{1-x}AL_{x}As$ alloys," Phys. Rev. B: Condens. Matter, Vol.24, No.6, pp.3295-3302, Sep., 1981.   DOI
4 W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less than 60 mV/dec," IEEE Electron Device Lett., Vol.28, No.8, Aug., 2007.
5 J. Knoch and J. Appenzeller, "Modeling of High- Performance p-Type III-V Heterojunction Tunnel FETs," IEEE Electron Device Lett., Vol.31, No.4, Apr., 2010.
6 P.-F. Guo, L.-T. Yang, Y. Yang, L. Fan, G.-Q. Han, G. S. Samudra, and Y.-C. Yeo, "Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current," IEEE Electron Device Lett., Vol.30, No.9, Sep., 2009.
7 W. Y. Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide- Semiconductor Field-Effect Transistors," Jpn. J. Appl. Phys., Vol.49, No.4, pp.04DJ12-1-04DJ12-3, Apr., 2010.   DOI
8 E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device Physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications," J. Appl. Phys., Vol.103, No.10, pp.104504-1-104504-5, May, 2008.   DOI   ScienceOn
9 K. Ganapathi and S. Salahuddin, "Heterojunctino Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High ON Current," IEEE Electron Device Lett., Vol.32, No.5, pp.689- 691, May, 2011.   DOI
10 ATLAS User's Manual, Silvaco International, Santa Clara, CA, Nov/Dec., 2008.
11 Process Integration, Devices & Structures (PIDS), International Technology Roadmap for Semiconductors (ITRS), 2009 edition.
12 Y. Apanovich, P. Blakey, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and A. Tcherniaev, "Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects," IEEE Trans. Electron Devices, Vol.42, No.2, pp.890-898, May, 1995.   DOI   ScienceOn
13 O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of Tunneling Field-Effect Transistors Using Strained -Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol.29, No.9, pp.1074-1077, Sep., 2008.   DOI   ScienceOn