• 전자공학회논문지 IE
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• v.44 no.2
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• pp.14-20
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• 2007

This paper presents quaternary D flip-flop with advanced performance. Quaternary D flip-flop is composed of the components such as thermometer code output circuit, EX-OR gate, bias inverter, transmission gate and binary D flip-flop circuit. The designed circuit is simulated by HSPICE in $0.35{\mu}m$ one-poly six-metal CMOS process parameters with a single +3.3V supply voltage. In the simulations, sampling frequencies is measured around 100MHz. The PDP parameters and FOM we estimated to be 59.3fJ, 33.7 respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.133-140
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• 1998

In this paper, RS coded DTMF modulation for reliable data transmission over mobile fading channels is considered. The circuits of (15,9) RS codec are proposed and synthesized, and the performances are evaluated over fading channels. The codec circuits take about 14000 gates standardized by 2-input NAMD gate. The (15,9) RS coded DTMF signalling provides theoretical coding gain more than 20 dB over fading channels for BER 10.6, the criterion for data transmissions in mobile communications such as IMT-2000. Thus, It is very effective to apply RS codec to DTMF signalling for data transmission in mobile communications over fading channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1939-1947
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• 1999

This paper proposes new line code BIM (Bit Insertion and Manipulation) that is designed to overcome the problems of existing line codes. The block code, one of typical existing line code, has good transmission performance but difficulty in implementation. The other typical existing line code, bit insertion code, is easy to implementation but has bad transmission performance. BIM code in this paper could provide not only good performance but also provides simplicity in the implementation by combining the good points of block code into it of bit insertion code properly. In this paper, 5B6B type BIM code is designed. Designed 5B6B BIM code shows good transmission performance such $\pm$2 DSV, 0 RSD, 7 maximum run length and also it can be implemented under 2000 gates and need only 1 bit redundancy.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• Journal of IKEEE
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• v.22 no.2
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• pp.484-487
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• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.191-197
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• 2005

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

• Journal of the Korean institute of surface engineering
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• v.32 no.6
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• pp.703-708
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• 1999

Silicides have been used extensively in ULSI logic device fabrication as contact materials for the active areas as well as the poly- Si gates. NiSi is a promising candidate for submicron device application due to less volume expansion, low formation temperature, little silicon consumption, and large stable processing temperature window. In this report, the microstructure of nickel silicides fabricated with a thermal evaporator has been investigated. We observed systematic transformation of Ni silicides of $Ni_2$Si, NiSi, $NiSi_2$, as annealing temperature increases. All the silicides have been identified by a X-ray diffractometer (XRD). The cross-sectional microstructure of silicides was examined by a transmission electron microscope (TEM) equipped with a energy dispersive spectrometer(EDS). The surface roughness of silicides was measured by scanning probe microscope(SPM). Although we observed thin oxide layer existed at the $Ni/NiSi_{x}$ interface, we fabricated successfully $550\AA$-thick planar Ni-monosilicide at the temperature range of$ 400~700^{\circ}C$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.