• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Bulletin of the Korean Chemical Society
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• v.35 no.3
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• pp.731-736
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• 2014

An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.36-39
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• 2002

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays (AMLCD), allowing the integration of both active matrix and driving circuit on the same substrate (normally glass). As high temperature process is not used for glass substrate because of the low softening points below 450$^{\circ}C$. However, high temperature process is required for getting high crystallization volume fraction (i.e. crystallinity). A poly-Si thin film transistor has been fabricated to investigate the effect of high temperature process on the molybdenum (Mo) substrate. Improve of the crystallinity over 75% has been noticed. The properties of structural and electrical at high temperature poly-Si thin film transistor on Mo substrate have been also analyzed using a sputtering method

• Journal of IKEEE
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• v.17 no.4
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• pp.531-536
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• 2013

The impact of UV irradiation process on the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor was investigated. Due to the high intensity UV irradiation before the gate dielectric deposition, the conductivity of AlGaN/GaN structure and the drain saturation current of the transistor increased by about 10 %. However, the pinch off characteristics of transistor was severely deformed by the process. By comparing the electrical characteristics of the transistors, it was proposed that the high intensity UV irradiation formed a sub-channel under the two dimensional electron gas of AlGaN/GaN structure even without additional impurity injection.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.86-92
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• 1980

This paper dealt with an oscillator which can be integrated and 1 he switching characteristics of the transistor as a component of multistage switching circuits . The switching characteristics were analyzed by utilizing the base voletare and the charactistics of the minit step function. Taking the storage time of the transistor into consideration, the transistor is considered as a time delay device, and an integrable time delay circuit an osicillator are realized.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.539-542
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• 1987

This paper presents driving circuits technology to enable high speed drive of MOSFET, IGBT(Insulated Gate Bipolar Transistor) and SIT(Static Induction Transistor). In addition to, it demonstrates application circuits(high frequency resonant type inverters, ultrasonic power supply etc.) using the, developing drive circuits.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.276-280
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• 2003

This paper presents a zero voltage and zero current switching (ZVZCS) interleaving two-transistor forward converter for high input voltage and high power application. A phase shift has a disadvantage that a circulating current and RMS current stress, conduction losses of transformer and switching devices increases. Due to this circulating current and RMS current stress, conduction losses of transformer and switching devices increases. To alleviate these problems, we propose an improved interleaving two-transistor forward Zero Voltage and Zero Current Switching (ZVZCS) dc/dc converter using a tapped inductor a snubber capacitor and two snubber diodes attached at the secondary side of transformer. The proposed ZVZCS converter is verified on a 1.8kW, 5kHz experimental prototype.