JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

High Quality Vertical Silicon Channel by Laser-Induced Epitaxial Growth for Nanoscale Memory Integration

  • Son, Yong-Hoon (Semiconductor R&D center, Samsung Electronics Co., Ltd.) ;
  • Baik, Seung Jae (Department of Electrical, Electronic, and Control Engineering, Hankyong National University) ;
  • Kang, Myounggon (Semiconductor R&D center, Samsung Electronics Co., Ltd.) ;
  • Hwang, Kihyun (Semiconductor R&D center, Samsung Electronics Co., Ltd.) ;
  • Yoon, Euijoon (Department of Materials Science and Engineering, Seoul National University)
  • Received : 2013.11.14
  • Accepted : 2014.02.22
  • Published : 2014.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

Keywords

References

  1. K. Kim, Technical Digest of IEEE International Electron Device Meeting 2010, p. 1, 2010
  2. T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi, IEEE J. Solid-State Circuits, 37, pp.1510-1522, 2002 https://doi.org/10.1109/JSSC.2002.802359
  3. E. M. Vogel, Nature Nanotechnology, Vol.2, pp.25-32, 2006
  4. H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D. W. Kim, K. Hwang, J.-J. Shim, J. S. Lim, K.-H. Kim, S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U.-I. Chung, and W.-S. Lee, 2009 Symposium on VLSI Technology, pp. 192-193 (2009)
  5. S. Hall, C. H. De Groot, V. D. Kunz, and P. Ashburn, IEEE Transactions on Electron Devices, Vol. 51, Issue. 1, pp. 158-161 (2004) https://doi.org/10.1109/TED.2003.821378
  6. S. J. Ahn, G. H. Koh, K. W. Kwon, S. J. Baik, G. T. Jung, T. N. Hwang, H. S. Jeong, and K. Kim, Technical Digest of IEEE International Electron Devices Meeting 2003, pp.10.4.1-10.4.4 (2003)
  7. T. O. Sedgwick, M. Berkenblit, and T. S. Kuan, Applied Physics Letters, Vol. 54, Issue. 26, pp. 2689-2691 (1989) https://doi.org/10.1063/1.101036
  8. Y.-H. Son, S. J. Baik, S. Jeon, J.-W. Lee, G. Hwang, Y. G. Shin, and E. Yoon, IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp.3863-3868 (2011) https://doi.org/10.1109/TED.2011.2167333
  9. Y.-H. Son, J.-W. Lee, P. Kang, M.-G. Kang, J. B. Kim, S. H. Lee, Y.-P. Kim, I. S. Jung, B. C. Lee, S. Y. Choi, U.-I. Chung, J. T. Moon, and B.-I. Ryu, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 80-81, 2007
  10. J. S. Im, H. J. Kim and M. O. Thompson, Applied Physics Letters, Vol. 63, No. 14, pp. 1969-1971 (1993) https://doi.org/10.1063/1.110617
  11. V. V. Gupta, H. J. Song, and J. S. Im, Vol. 71, No. 1, pp.99-101, 1997 https://doi.org/10.1063/1.119481
  12. S. D. Brotherton, D. J. McCulloch, J. P. Gowers, J. R. Ayres, and M. J. Trainor, Journal of Applied Physics, Vol. 82, No. 8, pp.4086-4094, 1997 https://doi.org/10.1063/1.365719
  13. H.-L. Chen and C.-Y. Wu, IEEE transactions on electron devices, Vol. 45, No. 10, pp. 2245-2247, 1998 https://doi.org/10.1109/16.725260
  14. C. H. Kim, K-S. Sohn, and J. Jang, J. Appl. Phys. 81, pp.8084-8090, 1997 https://doi.org/10.1063/1.365416
  15. S. J. Baik, K. S. Lim, W. Choi, H. Yoo, J.-S. Lee, and H. Shin, Nanoscale, 3, pp. 2560-2565 (2011) https://doi.org/10.1039/c1nr10104h