• Title/Summary/Keyword: Top oxide

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A Study on the Effects of Micro Cavity on the HTL Thicknesses on the Top Emission Organic Light Emitting Diode (유기발광 다이오드의 정공수송층 두께에 따른 미소 공진 효과의 영향에 관한 연구)

  • Lee, DongWoon;Cho, Eou Sik;Seong, Jin-Wook;Kwon, Sang Jik
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.1
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    • pp.91-94
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    • 2022
  • Top emission organic light-emitting diode is commonly used because of high efficiency and good color purity than bottom - emission organic light-emitting device. Unlike BEOLED, TEOLED contain semi-transparent metal cathode. Because of semi-transparent cathode, micro cavity effect occurs in TEOLED. We optimized this effect by changing the thickness of hole injection layer. Device consists of is indium-tin-oxide / N,N'-Di-[(1-naphthyl)-N,N'-diphenyl]-1,1'-biphenyl-4,4'-diamine (x nm) / tris-(8-hydroxyquinoline) aluminum (50nm) / LiF(0.5nm) / Mg:Ag (1:9), and we changed NPB thickness which is used as HTL in our device in order to study how micro cavity effects are changed by optical path. As the results, NPB thickness at 35nm showed the current efficiency of 8.55Cd/A.

Characterizations of Interface-state Density between Top Silicon and Buried Oxide on Nano-SOI Substrate by using Pseudo-MOSFETs

  • Cho, Won-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.2
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    • pp.83-88
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    • 2005
  • The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

Fabrication of Novel Thin Film Diode with Multi-step Anodic Oxidation and Post Heat-treatment

  • Hong, Sung-Jei;Lee, Chan-Jae;Moon, Dae-Gyu;Kim, Won-Keun;Han, Jeong-In
    • Transactions on Electrical and Electronic Materials
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    • v.3 no.4
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    • pp.27-31
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    • 2002
  • Thin film diode with reliable interfacial structure was fabricated by using multi-step anodic oxidation. The thickness of the oxide layer was preciously controlled with anodic voltage. Also, interfacial structure between oxide layer and top electrode was improved by applying post heat-treatment. The thin film diode showed symmetric and stable I-V characteristics after the post heat-treatment.

Mass Transfer Experiments for the Heat Load During In-Vessel Retention of Core Melt

  • Park, Hae-Kyun;Chung, Bum-Jin
    • Nuclear Engineering and Technology
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    • v.48 no.4
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    • pp.906-914
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    • 2016
  • We investigated the heat load imposed on the lower head of a reactor vessel by the natural convection of the oxide pool in a severe accident. Mass transfer experiments using a $CuSO_4-H_2SO_4$ electroplating system were performed based on the analogy between heat and mass transfer. The $Ra^{\prime}_H$ of $10^{14}$ order was achieved with a facility height of only 0.1 m. Three different volumetric heat sources were compared; two had identical configurations to those previously reported, and the other was designed by the authors. The measured Nu's of the lower head were about 30% lower than those previously reported. The measured angular heat flux ratios were similar to those reported in existing studies except for the peaks appearing near the top. The volumetric heat sources did not affect the Nu of the lower head but affected the Nu of the top plate by obstructing the rising flow from the bottom.

AZO Transparent Electrodes for Semi-Transparent Silicon Thin Film Solar Cells (AZO 투명 전극 기반 반투명 실리콘 박막 태양전지)

  • Nam, Jiyoon;Jo, Sungjin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.6
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    • pp.401-405
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    • 2017
  • Because silicon thin film solar cells have a high absorption coefficient in visible light, they can absorb 90% of the solar spectrum in a $1-{\mu}m$-thick layer. Silicon thin film solar cells also have high transparency and are lightweight. Therefore, they can be used for building integrated photovoltaic (BIPV) systems. However, the contact electrode needs to be replaced for fabricating silicon thin film solar cells in BIPV systems, because most of the silicon thin film solar cells use metal electrodes that have a high reflectivity and low transmittance. In this study, we replace the conventional aluminum top electrode with a transparent aluminum-doped zinc oxide (AZO) electrode, the band level of which matches well with that of the intrinsic layer of the silicon thin film solar cell and has high transmittance. We show that the AZO effectively replaces the top metal electrode and the bottom fluorine-doped tin oxide (FTO) substrate without a noticeable degradation of the photovoltaic characteristics.

Metal-Oxide-Silicon (MOS) 구조에서 중수소 이온 주입된 게이트 산화막의 절연 특성

  • Seo, Yeong-Ho;Do, Seung-U;Lee, Yong-Hyeon;Lee, Jae-Seong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.6-6
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    • 2009
  • We present an alternative process whereby deuterium is delivered to the location where the gate oxide reside by an implantation process. Deuterium ions were implanted using different energies to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas was performed to remove the D-implantation damage. We have observed that deuterium ion implantation into the gate oxide region can successfully remove the interface states and the bulk defects.

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The Charge Trapping Properties of ONO Dielectric Films (재산화된 질화산화막의 전하포획 특성)

  • 박광균;오환술;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.8
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    • pp.56-62
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    • 1992
  • This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

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Dielectrophoretic Alignment and Pearl Chain Formation of Single-Walled Carbon Nanotubes in Deuterium Oxide Solution

  • Lee, Dong Su;Park, Yung Woo
    • Carbon letters
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    • v.13 no.4
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    • pp.248-253
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    • 2012
  • Dielectrophoretic filtering and alignment of single-walled carbon nanotubes (SWCNTs) were tested using deuterium oxide as a solvent. A solution of deuterium oxide-SWCNTs was dropped on top of a silicon chip and an ac electric field was applied between pre-defined electrodes. Deuterium oxide was found to be a better solvent than hydrogen oxide for the dielectrophoresis process with higher efficiency of filtering. This was demonstrated by comparing Raman spectra measured on the initial solution with those measured on the filtered solution. We found that the aligned nanotubes along the electric field were not deposited on the substrate but suspended in solution, forming chain-like structures along the field lines. This so-called pearl chain formation of CNTs was verified by electrical measurements through the aligned tubes. The solution was frozen in liquid nitrogen prior to the electrical measurements to maintain the chain formation. The current-voltage characteristics for the sample demonstrate the existence of conduction channels in the solution, which are associated with the SWCNT chain structures.

The Effect of Mo Addition on Oxygen Vacancies in the Oxide Scale of Ferritic Stainless Steel for SOFC Interconnects

  • Dae Won Yun;Hi Won Jeong;Seong Moon Seo;Hyung Soo Lee;Young Soo Yoo
    • Corrosion Science and Technology
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    • v.23 no.1
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    • pp.33-40
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    • 2024
  • The concentration and diffusion coefficient of oxide ion vacancies in the oxide scale formed on Fe-22Cr-0.5Mn ferritic stainless steel with and without molybdenum (Mo) was measured at 800℃ by the electrochemical polarization method. After pre-oxidation for 100 h in ambient air at 800 ℃, the oxide scale on one side was completely removed with sandpaper. A YSZ plate was placed on the side where the oxide scale remained. Platinum (Pt) meshes were attached on the top of the YSZ plate and the side where the oxide scale was removed. Changes in electrical current were measured after applying an electrical potential through Pt wires welded to the Pt meshes. The results were interpreted by solving the diffusion equation. The diffusion coefficient and concentration of oxide ion vacancy decreased by 30% and 70% in the specimen with Mo, respectively, compared to the specimen without Mo. The oxide ion vacancy concentration of chromia decreased due to the addition of Mo.

High Performance nFET Operation of Strained-SOI MOSFETs Using Ultra-thin Strained Si/SiGe on Insulator(SGOI) Substrate (초고속 구동을 위한 Ultra-thin Strained SGOI n-MOS 트랜지스터 제작)

  • 맹성렬;조원주;오지훈;임기주;장문규;박재근;심태헌;박경완;이성재
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1065-1068
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    • 2003
  • For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

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