• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• Journal of Welding and Joining
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• v.27 no.3
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• pp.17-22
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.243.2-243.2
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• 2009

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.101-104
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• 2018

An electric field was applied to a Mo conductive layer in the sandwiched structure of $glass/SiO_2/Mo/SiO_2/a-Si$ to induce Joule heating in order to generate the intense heat needed to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced via Joule heating through a solid state transformation. Blanket crystallization was accomplished within the range of millisecond, thus demonstrating the possibility of a new crystallization route for amorphous silicon films. The grain size of JIC poly-Si can be varied from few tens of nanometers to the one having the larger grain size exceeding that of excimer laser crystallized (ELC) poly-Si according to transmission electron microscopy. We report here the blanket crystallization of amorphous silicon films using the $2^{nd}$ generation glass substrate.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Korean Journal of Metals and Materials
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• v.48 no.11
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.