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C. Liu, T. Song, J. Cho, J. Kim, J. Kim, and S. K. Lim, "Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC," in Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference, New York, NY, pp. 783-788, 2011.
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M. Jung, J. Mitra, D. Z. Pan, and S. K. Lim, "TSV stress-aware fullchip mechanical reliability analysis and optimization for 3D IC," in Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference, New York, NY, pp. 188-193, 2011.
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M. Jung, X. Liu, S. K. Sitaraman, D. Z. Pan, and S. K. Lim, "Fullchip through-silicon-via interfacial crack analysis and optimization for 3D IC," in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 563-570, 2011.
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J. S. Yang, K. Athikulwongse, Y. J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proceedings of the 47th ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 803-806, 2010.
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K. Athikulwongse, A. Chakraborty, J. S. Yang, D. Z. Pan, and S. K. Lim, "Stress-driven 3D-IC placement with TSV keep-out zone and regularity study," in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 669-674, 2010.
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T. Song and S. K. Lim, "A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC," in Proceedings of the 20th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, CA, pp. 239-242, 2011.
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X. Zhao, M. Scheuermann, and S. K. Lim, "Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs," in Proceedings of the 49th ACM/EDAC/IEEE Design Automation Conference, San Francisco, CA, pp. 157-162, 2012.
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