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http://dx.doi.org/10.6117/kmeps.2014.21.4.091

Cu-Filling Behavior in TSV with Positions in Wafer Level  

Lee, Soon-Jae (Department of Materials Science and Engineering, University of Seoul)
Jang, Young-Joo (Department of Materials Science and Engineering, University of Seoul)
Lee, Jun-Hyeong (Department of Materials Science and Engineering, University of Seoul)
Jung, Jae-Pil (Department of Materials Science and Engineering, University of Seoul)
Publication Information
Journal of the Microelectronics and Packaging Society / v.21, no.4, 2014 , pp. 91-96 More about this Journal
Abstract
Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.
Keywords
through silicon via; Cu-filling; Electroplating; Si wafer; Filling ratio;
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Times Cited By KSCI : 6  (Citation Analysis)
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