• Journal of Welding and Joining
• /
• v.32 no.3
• /
• pp.68-73
• /
• 2014

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

• Korean Chemical Engineering Research
• /
• v.47 no.1
• /
• pp.1-10
• /
• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of electromagnetic engineering and science
• /
• v.11 no.4
• /
• pp.282-289
• /
• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• Journal of the Korean Ceramic Society
• /
• v.35 no.12
• /
• pp.1329-1336
• /
• 1998

A twt -step carbothermal reduction scheme has been employed for the synthesis of SiC whiskers in an Ar or a H2 atmosphere via vapor-solid two-stage and vapor-liquid-solid growth mechanism respectively. It has been shown that the whisker growth proceed through the following reaction mechanism in an Ar at-mosphere : SiO2(S)+C(s)-SiO(v)+CO(v) SiO(v)3CO(v)=SiC(s)whisker+2CO2(v) 2C(s)+2CO2(v)=4CO(v) the third reaction appears to be the rate-controlling reaction since the overall reaction rates are dominated by the carbon which is participated in this reaction. The whisker growth proceeded through the following reaction mechaism in a H2 atmosphere : SiO2(s)+C(s)=SiO(v)+CO(v) 2C(s)+4H2(v)=2CH4(v) SiO(v)+2CH4(v)=SiC(s)whisker+CO(v)+4H2(v) The first reaction appears to be the rate-controlling reaction since the overall reaction rates are enhanced byincreasing the SiO vapor generation rate.

• Journal of the Optical Society of Korea
• /
• v.17 no.4
• /
• pp.317-322
• /
• 2013

We have proposed and demonstrated a low numerical aperture technique to measure the depth of through silicon vias (TSVs) using white-light scanning interferometry. The high aspect ratio hole like TSV's was considered to be impossible to measure using conventional optical methods due to low visibility at the bottom of the hole. We assumed that the limitation of the measurement was caused by reflection attenuation in TSVs. A novel interference theory which takes the structural reflection attenuation into consideration was proposed and simulated. As a result, we figured out that the low visibility in the interference signal was caused by the unbalanced light intensity between the object and the reference mirror. Unbalanced light can be balanced using an aperture at the illumination optics. As a result of simulation and experiment, we figured out that the interference signal can be enhanced using the proposed technique. With the proposed optics, the depth of TSVs having an aspect ratio of 11.2 was measured in 5 seconds. The proposed method is expected to be an alternative method for 3-D inspection of TSVs.

• ETRI Journal
• /
• v.40 no.6
• /
• pp.759-773
• /
• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.4
• /
• pp.45-49
• /
• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• Journal of Welding and Joining
• /
• v.31 no.3
• /
• pp.11-16
• /
• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• Journal of Sensor Science and Technology
• /
• v.22 no.2
• /
• pp.130-135
• /
• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.1
• /
• pp.108-113
• /
• 2022

The deep-learning-based measurement method with the through-focus scanning optical microscopy (TSOM) estimated the size of the object using the classification. However, the measurement performance of the method depends on the number of subdivided classes, and it is practically difficult to prepare data at regular intervals for training each class. We propose an approach to measure the size of an object in the TSOM image using the deep-learning regression model instead of using classification. We attempted our proposed method to estimate the top critical dimension (TCD) of through silicon via (TSV) holes with 2461 TSOM images and the results were compared with the existing method. As a result of our experiment, the average measurement error of our method was within 30 nm (1σ) which is 1/13.5 of the sampling distance of the applied microscope. Measurement errors decreased by 31% compared to the classification result. This result proves that the proposed method is more effective and practical than the classification method.