GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections |
Pak, Jun-So
(Dept. of Electrical Engineering, KAIST)
Cho, Jong-Hyun (Dept. of Electrical Engineering, KAIST) Kim, Joo-Hee (Dept. of Electrical Engineering, KAIST) Kim, Ki-Young (Dept. of Electrical Engineering, KAIST) Kim, Hee-Gon (Dept. of Electrical Engineering, KAIST) Lee, Jun-Ho (Advanced Design Team, Hynix Semiconductor Inc.) Lee, Hyung-Dong (Advanced Design Team, Hynix Semiconductor Inc.) Park, Kun-Woo (Advanced Design Team, Hynix Semiconductor Inc.) Kim, Joung-Ho (Dept. of Electrical Engineering, KAIST) |
1 | J. S. Pak, J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, "Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor structure through silicon via in signal propagation and power delivery in 3D chip package," Proc. of the 60th Electronic Components and Technology Conference 2010 (ECTC 2010), Las Vegas, USA, Jun. 2010. |
2 | J. S. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, "PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models," the IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 1, no. 2, pp. 208-219, Feb. 2011. DOI ScienceOn |
3 | Sandra Winkler, Advanced IC Packaging, 2007 Edition, Electronic Trend Publications. 2007. |
4 | S. Linder, H. Baltes, F. Gnaedinger, and E. Doering, "Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers," in Proc. MEMS, pp. 349-354, 1994. |
5 | L. L. W. Leung, K. J. Chen, "Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates," IEEE Transaction on Microwave Theory and Techniques, vol. 53, no. 8, pp. 2472-2480, Aug. 2005. DOI ScienceOn |
6 | U. Kang, et al., "8 Gb 3-D DDR3 DRAM using through- silicon-via technology," IEEE Journal of Solid- State Circuit, vol. 45, no. 1, Jan. 2010. |
7 | C. Ryu, D. Chung, Junho Lee, K. Lee, T. Oh, and J. Kim, "High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package," IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 151-154, Oct. 2005. |
8 | J. S. Pak, C. Ryu, and J. Kim, "Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation," in Proceedings of the 9th International Symposium on Electronic Materials and Packaging, Daejeon, Korea, Nov. 2007. |
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