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Parasitic Capacitance Analysis with TSV Design Factors  

Seo, Seong-Won (Electronic Packaging Research Center, Kangnam University)
Park, Jung-Rae (Electronic Packaging Research Center, Kangnam University)
Kim, Gu-Sung (Electronic Packaging Research Center, Kangnam University)
Publication Information
Journal of the Semiconductor & Display Technology / v.21, no.4, 2022 , pp. 45-49 More about this Journal
Abstract
Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.
Keywords
TSV; Parasitic capacitor; Design factor; Memory; Package;
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Times Cited By KSCI : 1  (Citation Analysis)
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