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Trend and Prospect for 3Dimensional Integrated-Circuit Semiconductor Chip  

Kwon, Yongchai (Department of Chemical and Environmental Technology, Inha Technical College)
Publication Information
Korean Chemical Engineering Research / v.47, no.1, 2009 , pp. 1-10 More about this Journal
Abstract
As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.
Keywords
3D IC Chip; RC Delay; Through Silicon Via; Vertical Interconnect;
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Times Cited By KSCI : 1  (Citation Analysis)
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