• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.446-450
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• 2011

Tunable SC(Switched Capacitor) bandpass ${\Sigma}-{\Delta}$(Sigma-Delta) modulator used in wireless system receiver occurs a signal attenuation according to tuning of center frequency in signal bandwidth. In this paper, tunable bandpass 4th order SC bandpass ${\Sigma}-{\Delta}$ modulator with novel structure is proposed for rejection of signal attenuation in signal bandwidth. The existing structure uses a ten variable coefficient values for rejection of signal reduction in the modulator. But the proposed structure only use a two variable coefficient values for rejection of signal attenuation in the modulator. Also, an adder and comparator is replaced with a comparator having 4 inputs in the modulator. Therefore, the existing structure has one more OP-AMP. The purposed modulator was designed in $0.18\;{\mu}m$ CMOS technology. The resolution of the modulator within 310 kHz bandwidth and 40 MHz sampling frequency under 6.67 MHz, 10 MHz and 13.33 MHz intermediate frequency are over 10 bit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.3
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• pp.31-35
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• 2009

In this paper, tunable 4th order SC(switched capacitor) bandpass ${\sigma}-{\Delta}$(Sigma-Delta) modulator with advanced architecture that can adjust the IF by two coefficient values is proposed for data conversion in the wireless communication. Its architecture can optionally adjust all the 4th order noise transfer function in comparison with the conventional architecture. In order to adjust the IF, the conventional architecture needs the four variable coefficients values, basic clocks and eight clocks. On the other hand, the proposed architecture can adjust the IF by two variable coefficient values and basic clocks only.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.294-301
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• 2017

This paper presents a low power ${\Sigma}{\Delta}$ modulator for an implantable chip to acquire a bio-signal such as EEG, DBS, and EMG. In order to reduce a power consumption of the proposed fourth order modulator, two op-amps utilized for the first two integrators are reconfigured to drive the second two integrators. The KT/C noise reduction circuit in the first two integrators is employed to enhance SNR of the modulator. The proposed circuit was fabricated in a 0.18 um CMOS n-well 1 poly 6 metal process with the active chip core area of $900um{\times}800um$ and the power consumption of 830 uW. Measurement results were demonstrated to be SNDR of 76 dB, DR of 77 dB, ENOB of 12.3 bit at the input frequency of 250 Hz and the clock frequency of 256 kHz. FOM1 and FOM2 were measured to be 41 pJ/step and 142.4 dB, respectively.

• IMMUNE NETWORK
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• v.15 no.2
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• pp.100-109
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• 2015

Controlling balance between T-helper type 1 (Th1) and T-helper type 2 (Th2) plays a pivotal role in maintaining the biological rhythm of Th1/Th2 and circumventing diseases caused by Th1/Th2 imbalance. Interleukin 4 (IL-4) is a Th2-type cytokine and often associated with hypersensitivity-related diseases such as atopic dermatitis and allergies when overexpressed. In this study, we have tried to elucidate the function of 1-palmitoyl-2-linoleoyl-3-acetyl-rac-glycerol (EC-18) as an essential modulator of Th1/Th2 balance. EC-18 has showed an inhibitory effect on the production of IL-4 in a dose-dependent manner. RT-PCR analysis has proved EC-18 affect the transcription of IL-4. By analyzing the phosphorylation status of Signal transducer and activator of transcription 6 (STAT6), which is a transcriptional activator of IL-4 expression, we discovered that EC-18 induced the decrease of STAT6 activity in several stimulated cell lines, which was also showed in STAT6 reporter analysis. Co-treatment of EC-18 significantly weakened atopy-like phenotypes in mice treated with an allergen. Collectively, our results suggest that EC-18 is a potent Th2 modulating factor by regulating the transcription of IL-4 via STAT6 modulation, and could be developed for immune-modulatory therapeutics.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.507-508
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• 2006

High performance delta-sigma modulator is developed for audio-codec applications(i.e.. 16-bit resolution at a 20kHz signal bandwidth). The modulator is realized with fully-differential switched capacitor integrators. All stages employ a single-stage folded-cascode amplifier. The presented delta-sigma modulator when clocked at 3.2MHz achieves 85.2dB peak-SNDR and 94.8dB SNR. This modulator is designed in a SAMSUNG $0.18{\mu}m$ CMOS process. Finally, this paper shows the test setup and FFT result gained from delta-sigma modulator chip designed for audio applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.