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http://dx.doi.org/10.5573/ieie.2017.54.5.24

Design of Low Power 4th order ΣΔ Modulator with Single Reconfigurable Amplifier  

Sung, Jae-Hyeon (Department of Electronic Engineering, Inha University)
Lee, Dong-Hyun (Department of Electronic Engineering, Inha University)
Yoon, Kwang Sub (Department of Electronic Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.54, no.5, 2017 , pp. 24-32 More about this Journal
Abstract
In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.
Keywords
CMOS; Delta-Sigma Modulator; Low Power; Bio Signal Processing;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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