• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• Annual Conference of KIPS
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• 2009.04a
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• pp.7-10
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• 2009

본 연구에서는 차량 네트워크를 구성하는 CAN(Controller Area Network), MOST(Media Oriented System Transport)등의 버스 시스템을 중심으로 IVN(In-Vechicle Network)에 대한 선행연구와 지능형 통합 Gateway 개발 연구를 통해 통합적인 차량 상태정보 수집 및 교환을 위한 차량 Gateway를 제시하고, Soc(System on Chip)형태의 차량용 인터페이스(HMI, Human Machine Interface)를 통한 지능형 통합 GateWay 통신 기술을 OSGi의 번들 형태로 제작하여 알아본다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.273-279
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• 2001

This paper describes a design and implementation of ISDN system on a chip which provides ISDN service and used to develop a low-price multimedia communication terminal. This ISDN SOC is an ISDN system control chip which has 32bit RISC processor, and it includes ISDN S interface transceiver, G.711 voice CODEC, PC interface for data communication, ISDN protocol which includes Q.931 call control protocol and internet protocol. It provides good solution to develope ISDN terminal equipment and ISDN terminal adaptor which connected with basic rate interface, because it minimize external peripheral devices.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Smart Structures and Systems
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• v.12 no.1
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• pp.23-39
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• 2013

In this article, a smart multifunctional optical system-on-a-chip (SOC) sensor platform is presented and its application for fiber Bragg grating (FBG) sensor interrogation in optical sensor networks is investigated. The smart SOC sensor platform consists of a superluminescent diode as a broadband source, a tunable microelectromechanical system (MEMS) based Fabry-P$\acute{e}$rot filter, photodetectors, and an integrated microcontroller for data acquisition, processing, and communication. Integrated with a wireless sensor network (WSN) module in a compact package, a smart optical sensor node is developed. The smart multifunctional sensor platform has the capability of interrogating different types of optical fiber sensors, including Fabry-P$\acute{e}$rot sensors and Bragg grating sensors. As a case study, the smart optical sensor platform is demonstrated to interrogate multiplexed FBG strain sensors. A time domain signal processing method is used to obtain the Bragg wavelength shift of two FBG strain sensors through sweeping the MEMS tunable Fabry-P$\acute{e}$rot filter. A tuning range of 46 nm and a tuning speed of 10 Hz are achieved. The smart optical sensor platform will open doors to many applications that require high performance optical WSNs.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.223-226
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• 2003

We propose an improvement method for a $\underline{G}ate$ $\underline{OX}ide(GOX)$ thinning at the edge of $\underline{S}hallow$ $\underline{T}rench$ $\underline{I}solation(STI)$, when STI is adopted to Dual Gate Oxide(DGOX) Process. In the case of SOC(System On-a-Chip), the DGOX process is usually used for realizing both a low and a high voltage parts in one chip. However, it is found that the severe GOX thinning occurs from at STI top edge region and a dent profile exists at the top edge of STI, when conventional DGOX and STI process carried out in high density device chip. In order to overcome this problem, a new DGOX process is tried in this study. And we are able to prevent the GOX thinning by H2 anneal, partially SiN liner skip, and a method which is merged a thick sidewall oxide(S/O) with a SiN pull-back process. Therefore, a good subthreshold characteristics without a double hump is obtained by the prevention of a GOX thinning and a deep dent profile.