JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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FeRAM Technology for System on a Chip

  • Kang, Hee-Bok (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Jeong, Dong-Yun (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Lom, Jae-Hyoung (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Oh, Sang-Hyun (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Lee, Seaung-Suk (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Hong, Suk-Kyoung (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Kim, Sung-Sik (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Park, Young-Jin (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.) ;
  • Chung, Jin-Young (FeRAM at the Memory R&D Center in Hynix Semiconductor Inc.)
  • Published : 2002.06.01
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Abstract

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

Keywords

References

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