DOI QR코드

DOI QR Code

Design and Implementation of Hardware for various vision applications

컴퓨터 비전응용을 위한 하드웨어 설계 및 구현

  • 양근탁 (제주대학교 전산통계학과) ;
  • 이봉규 (제주대학교 전산통계학과)
  • Received : 2010.07.26
  • Accepted : 2010.11.10
  • Published : 2011.01.01

Abstract

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

Keywords

References

  1. J. Yang, X. Chen, W. Kunz, "A PDA-based Face Recognition System", Proceedings of WACV 2002, 2002.
  2. Jong Bae Kim, "A personal identity annotation overlay system using a wearable computer for augmented reality," IEEE Transactions on Consumer Electronics, vol. 49, no. 4, pp. 1457-1467, Nov., 2003. https://doi.org/10.1109/TCE.2003.1261254
  3. E. Foxlin and L. Naimark, "VIS-Tracker : A Wearable Vision-Inertial Self-Tracker," IEEE VR2003, March, 2003.
  4. H. Nakajima, Y. Matsuo, M. Nagata and K. Saito, "Portable Translator capable of Recognizing Characters on Signboard and Menu Captured by built-in camera," Proc. of the ACL Interactive Poster and Demonstration Sessions, pp. 61 - 64, June, 2005.
  5. P. J. Burt and E. H. Adelson, "The Laplacian pyramid as a compact image code," IEEE Transactions on communications, vol. 31, no.4, pp. 532-540, April, 1983. https://doi.org/10.1109/TCOM.1983.1095851
  6. Kah-Kay Sung. Learning and Example Selection for Object and Pattern Detection. PhD thesis, MIT AI Lab, January 1996. Available as AI Technical Report 1572.
  7. J. Y. Kim, L. S. Kim, S. H. Hwang, "An Advanced Contrast Enhancement Using Partially Overlapped Sub-Block Histogram Equalization," IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no.4, pp. 475-484, 2001. https://doi.org/10.1109/76.915354
  8. P. G.. D. Valle, D. Atienza, G. Paci and F. Poletti, "Application of FPGA Emulation to SoC Floorplan and Packaging Exploration," XXII Conference on Design of Circuits and Integrated System, pp. 236-240.
  9. Theocharides, G. Link, N.Vijaykrishnan, M. J. Irwinand W. Wolf, "Embedded Hardware Face Detection", Proceedings of th 17thInternational Conference on VLSI Design (VLSID'04), Jan., 2004.
  10. O. Sims and J. Irvine, "An FPGA implementation of pattern-selective pyramidal image fusion," Proceedings of 2006 international conference of field programmable logic and application, Mardrid, Spain, August 2006.
  11. Z. Salcic, J. Sivaswamy, "IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework," Real-Time Imaging, vol. 5, no. 6, pp. 385-395, 1999. https://doi.org/10.1006/rtim.1998.0134
  12. LEON2 processor user's manual, Gaisler Research, http://www.gaisler.com
  13. MT9V112 manual, Micron Technology Inc., http://www.micron.com
  14. A. Kumar and B. Yegnanaarayana, "Template Matching Approach for Pose Problem in Face Verification," MRCS 2006, LNCS 4105, pp. 191-198, 2006